Semiconductor booster circuit having cascaded MOS transistors

Details Semiconductor booster circuit having cascaded MOS transistors Semiconductor booster circuit having cascaded MOS transistors

2006-09-05

2006-09-05

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S537000, C327S566000

Reexamination Certificate

active

07102422

ABSTRACT:
The semiconductor booster circuit includes a plurality of stages, each of which has a MOS transistor and two capacitors. The MOS transistor, having a drain, a source and a gate, is formed in a well of a substrate portion. One capacitor has a terminal connected to the drain of the MOS transistor, while the other capacitor has a terminal connected to the gate of the MOS transistor. A first clock signal generating means generate a first clock signal via another terminal of one capacitor. A second clock signal generating mean s generate a second clock signal, with a larger amplitude than a power supply voltage, via another terminal of another capacitor. The plurality of stages are cascaded together, and in each of the stages the source of the MOS transistor is electrically connected to the well in which the transistor is formed, while the wells are electrically insulated from each other.

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