Semiconductor bonding pad structure

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond

Reexamination Certificate

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Details

C257S786000

Reexamination Certificate

active

11432373

ABSTRACT:
The invention provides a bonding pad structure. At least one lower circuit layer is disposed overlying the substrate, wherein the lower circuit layer is a layout of circuit under pad. A top circuit layer is disposed overlying the lower circuit layer, wherein the top circuit layer comprises a top interconnect dielectric layer and a top interconnect pattern in the top interconnect dielectric layer. A top connecting layer is disposed overlying the top circuit layer, electrically connecting the top interconnect pattern. A top pad layer is disposed overlying the top connecting layer. A bonding ball is disposed overlying the top pad layer, wherein sides of the top interconnect pattern do not overlap a region extending inwardly and outwardly from a boundary of the bonding ball within distance of about 2.5μm.

REFERENCES:
patent: 6560862 (2003-05-01), Chen et al.
patent: 6900541 (2005-05-01), Wang et al.
patent: 7115985 (2006-10-01), Antol et al.
patent: 2005/0116345 (2005-06-01), Murtuza
patent: 2005/0258549 (2005-11-01), Mathew
patent: 2006/0071350 (2006-04-01), Fan et al.
patent: 2006/0154469 (2006-07-01), Hess et al.
patent: 2006/0154470 (2006-07-01), Pozder et al.

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