Semiconductor assembly for improved device warpage and...

Details Semiconductor assembly for improved device warpage and... Semiconductor assembly for improved device warpage and...

2007-07-17

2007-07-17

Tran, Long K. (Department: 2818)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Including adhesive bonding step

C438S106000, C438S455000, C438S457000, C257S783000, C257SE21122, C257SE21480

Reexamination Certificate

active

11253940

ABSTRACT:
A semiconductor device with a chip (505), its position defining a plane, and an insulating substrate (503) with first and second surfaces; the substrate is substantially coplanar with the chip, without warpage. One of the chip sides is attached to the first substrate surface using adhesive material (504), which has a thickness. The thickness of the adhesive material is distributed so that the thickness (504b) under the central chip area is equal to or smaller than the material thickness (504a) under the peripheral chip areas. Encapsulation compound (701) is embedding all remaining chip sides and the portions of the first substrate surface, which are not involved in the chip attachment. When reflow elements (720) are attached to the substrate contact pads, they are substantially coplanar with the chip.

REFERENCES:
patent: 2001/0005602 (2001-06-01), Mimata et al.
patent: 2003/0052419 (2003-03-01), Ujiie et al.

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