Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Subsequent separation into plural bodies
Reexamination Certificate
2001-08-03
2002-08-06
Fahmy, Jr., Wael (Department: 2823)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Subsequent separation into plural bodies
C438S409000, C438S413000, C438S406000, C438S759000
Reexamination Certificate
active
06429095
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to a method of manufacturing a semiconductor article to be suitably used for preparing a semiconductor device, a filter, a light emitting device, a micromechanical or optical part and, more particularly, it relates to a method of manufacturing a semiconductor article comprising a step of separating a multilayer structure having a porous layer into two or more than two parts.
2. Related Background Art
Semiconductor articles refer to semiconductor wafers, semiconductor substrates and other semiconductor members. For the purpose of the present invention, semiconductor articles include those on which one or more than one semiconductor devices are formed or to be formed by utilizing the semiconductor region thereof.
Certain semiconductor articles comprise a semiconductor layer formed on an insulator. Such semiconductor articles will be discussed in greater detail below. The technology of forming a single-crystal Si semiconductor layer on an insulator is known as the semiconductor on insulator (SOI) technology and has been investigated by many researchers because it provides a number of advantages that cannot be obtained by bulk Si substrates that are widely used for preparing ordinary Si integrated circuits. In short, the SOI technology provides advantages of:
(1) easy dielectric separation and feasibility to a high degree of integration;
(2) an excellent radiation resistance;
(3) a reduced floating capacitance and adaptability to high speed operation;
(4) capability of omitting a well step;
(5) prevention of latch-ups; and
(6) capability of producing fully depleted type field effect transistors as a result of realizing a semiconductor thin film.
Meanwhile, Japanese Patent Application Laid-Open No. 5-21338 and U.S. Pat. No. 5,371,037 propose a method of manufacturing a semiconductor article comprising a bonding step as will be described below.
According to the proposed method, a non-single-crystal semiconductor layer is formed on a porous layer and bonded to a support substrate with an insulation layer interposed therebetween and subsequently the porous layer is removed by etching. This method is unique and remarkable in that it provides an excellent uniformity for the film thickness of the SOI layer, a particular easiness for reducing the crystal defect density of the SOI layer, a good surface smoothness of the SOI layer, no need for a particularly specified and hence costly manufacturing apparatus and the capability of manufacturing SOI structures over a wide range of film thickness between several hundred angstroms and 10 microns.
Japanese Patent Application Laid-Open No. 9-102594 proposes a manufacturing method comprising forming a diffusion region by diffusing an element capable of controlling the conductivity into a silicon substrate, forming a porous layer in the diffusion region, forming a non-porous single-crystal layer in the diffusion region, bonding it to a supporting substrate with interposing an insulation layer and subsequently removing the porous layer. This method provides advantages that a relatively inexpensive resistance-non-specified substrate can be employed to reduce the manufacturing cost and that the concentration of the element (specific resistance) on and near the surface can be controlled precisely by the diffusion process. However, with the above proposed methods, a pair of silicon substrates are consumed for producing a single SOI wafer and one of the substrates will be totally lost as a result of grinding, polishing and etching.
Thus, Japanese Patent Application Laid-Open No. 7-302889 proposes a method of manufacturing an SOI wafer without losing a silicon substrate. The proposed method comprises forming a non-porous single-crystal semiconductor layer on a porous layer formed on a first substrate, bonding the non-porous single-crystal semiconductor layer to a second substrate with interposing an insulation layer, separating the first and second substrates along the porous layer without destroying the substrates, smoothing the surface of the first substrate and forming another porous layer on the first substrate for reuse. With this method, the first substrate is separated away without being destroyed so that it can be repeatedly used for the process of manufacturing SOI wafers to significantly reduce the manufacturing cost and simplify the manufacturing process.
However, the inventors of the present invention have found that, unless the first substrate is always separated to show the same contour and same (exposed) surface condition, the processing steps necessary for regenerating the first substrate to make it reuseable require certain adjustment.
Additionally, large undulations on the interface of the porous layer and the substrate can limit the reusability of the first substrate.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of manufacturing a semiconductor article at low cost with simplified processing steps necessary for regenerating a first substrate.
Another object of the present invention is to provide a method of manufacturing a semiconductor article adapted to separate a first substrate form a second article reliably and make it shown the same contour and same surface condition after the separation.
Still another object of the present invention is to provide a method of manufacturing a semiconductor article adapted to reduce the undulations on the porous layer/substrate interface of a first substrate after separating it from a second article and make the first substrate reusable regardless of its specific resistance.
According to the invention, the above objects and other objects are achieved by providing a method of manufacturing a semiconductor article comprising steps of forming a doped layer containing an element capable of controlling the conductivity type at least on one of the surfaces of a semiconductor substrate, modifying the surface of the doped layer into a porous state to obtain a porous layer thinner than the doped layer, forming a non-porous layer on the porous layer to prepare a first substrate, bonding said first article and a second article so as to produce a multilayer structure having said porous layer in the inside thereof, and separating said multilayer structure along said porous layer.
According to the invention, there is also provided a semiconductor article comprising a semiconductor substrate, a single-crystal semiconductor layer formed on the semiconductor substrate and a porous layer formed on the single-crystal semiconductor layer;
said single-crystal semiconductor layer being a layer formed by epitaxial growth;
said porous layer comprising a plurality of thin layers having respective porosities different from each other.
REFERENCES:
patent: 5371037 (1994-12-01), Yonehara
patent: 5453394 (1995-09-01), Yonehara et al.
patent: 5559043 (1996-09-01), Bruel
patent: 5856229 (1999-01-01), Sakaguchi et al.
patent: 6100165 (2000-08-01), Sakaguchi et al.
patent: 6121112 (2000-09-01), Sakaguchi et al.
patent: 6140209 (2000-10-01), Iwane et al.
patent: 6143628 (2000-11-01), Sato et al.
patent: 6190937 (2001-02-01), Nakagawa et al.
patent: 6221738 (2001-04-01), Sakaguchi et al.
patent: 6258698 (2001-07-01), Iwasaki et al.
patent: 0 499 488 (1992-08-01), None
patent: 0 757 377 (1997-02-01), None
patent: 0 767 486 (1997-04-01), None
patent: 0 793 263 (1997-09-01), None
patent: 0 797 258 (1997-09-01), None
patent: 0 843 345 (1998-05-01), None
patent: 5-21338 (1993-01-01), None
patent: 7-302889 (1995-11-01), None
patent: 9-102594 (1997-04-01), None
W. G. Howells, “Polymerblasting with Super-Water from 1974 to 1989: a Review”, Int'l J. Water Jet Tech., vol. 1, No. 1, pp. 1-16 (1990).
A. VanVeen, et al., “Helium-Induced Porous Layer Formation in Silicon”, Mat. Res. Soc. Symp. Proc., vol. 107, pp. 449-454 (1988).
A. Uhlir, “Electrolytic Shaping of Germanium and Silicon”, Bell Sys. Tech. J., vol. 35, pp. 333-347 (1956).
N. Sato, et al., “Epitaxial Growth of Porous Si for a New Bond and Etchback Silic
Sakaguchi Kiyofumi
Yonehara Takao
Fahmy Jr. Wael
Garcia Joannie Adelle
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