Semiconductor array device with single interconnection layer

Details Semiconductor array device with single interconnection layer Semiconductor array device with single interconnection layer

2003-08-01

2004-08-24

Abraham, Fetsum (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Ball or nail head type contact, lead, or bond

C257S503000, C257S700000, C257S734000, C257S776000, C257S781000

Reexamination Certificate

active

06781246

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a matrix-driven semiconductor array device, more particularly to its wire-bonding pads and their interconnections to the array elements.
2. Description of the Related Art
Semiconductor array devices are useful in opto-electronic printing apparatus. A typical semiconductor array device is a densely spaced linear array of light-emitting diodes (LEDs) formed in a semiconductor chip referred to as an LED array. The LEDs in the array are generally driven by another type of semiconductor array device, referred to as a driver integrated circuit (IC). The LED array is connected to the driver IC by fine wires bonded to pads on the array chip and the driver IC chip.
Simple interconnection schemes in which each LED in the array has its own bonding pad become difficult to implement at high array densities. This has led to matrix driving schemes such as the one illustrated in
FIG. 21
, which shows part of an LED array
100
disclosed in Japanese Unexamined Patent Application Publication No. 13-77431. The LEDs
101
are separated into groups of eight by isolation trenches
102
that divide the surface of the LED array
100
into electrically isolated semiconductor blocks
103
. Each semiconductor block
103
has a common electrode
104
formed near the row of LEDs
101
. Eight common interconnecting lines
105
run parallel to the array, crossing the block boundaries. The common electrodes
104
and common interconnecting lines
105
are covered by an interlayer dielectric film
106
.
Each LED
101
has an individual electrode
107
and an individual interconnecting line
108
. Each semiconductor block
103
includes a pair of electrode pads
109
,
110
. The individual interconnecting lines
108
and electrode pads
109
,
110
are formed on the interlayer dielectric film
106
, each individual interconnecting line
108
making contact with one of the common interconnecting lines
105
through an opening
111
in the interlayer dielectric film
106
. Electrode pad
110
is electrically coupled by an interconnecting lead
112
to the common electrode
104
in the same block. Electrode pad
109
is electrically coupled by an interconnecting lead
113
to one of the common interconnecting lines
105
. The interconnecting leads
112
,
113
are also formed on the interlayer dielectric film
106
.
This matrix interconnection structure enables a large number of LEDs
101
to be driven from a relatively small number of electrode pads
109
,
110
. A problem is that at the points at which the individual interconnecting lines
108
and interconnecting leads
112
,
113
cross the common electrodes
104
and common interconnecting lines
105
, short circuits can occur due to defects in the interlayer dielectric film
106
; such defects may arise from electrostatic breakdown or intrusion of foreign particles in the fabrication process. A further problem is that the interconnecting lines
108
and interconnecting leads
112
,
113
may become electrically open at vertical steps in the surface of the interlayer dielectric film
106
; the vertical steps are due to the thickness of the underlying common electrode pads
104
and common interconnecting lines
105
.
High fabrication cost is also a problem since, because compared to a single-layer interconnection process, a multi-layer interconnection process requires at least two additional photolithography steps to form the interlayer dielectric film and the upper layer of electrode pads and interconnecting lines.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a matrix interconnection structure for a semiconductor array device having only a single layer of interconnecting lines.
The invented semiconductor array device has a semiconductor layer disposed on a current-blocking layer. The semiconductor layer is partially covered by a dielectric film, and is divided into a plurality of mutually isolated parts. A first interconnecting pad overlies and is electrically coupled to one of these parts. A second interconnecting pad is disposed on the dielectric film.
A first group of semiconductor circuit elements is disposed in one or more of the mutually isolated parts of the semiconductor layer. These semiconductor circuit elements have electrodes that are electrically coupled to the first interconnecting pad by first conductive paths passing through the semiconductor layer.
A second group of semiconductor circuit elements is disposed in one or more other mutually isolated parts of the semiconductor layer. These semiconductor circuit elements have electrodes that are electrically coupled to the second interconnecting pad by second conductive paths insulated from the semiconductor layer by the dielectric film.
At least one of the second conductive paths crosses at least one of the first conductive paths at a point at which the first conductive path passes through the semiconductor layer. Preferably, all crossings of the first and second conductive paths are made in this way. The first and second interconnecting pads can then be coupled to the first and second groups of semiconductor circuit elements by a single layer of interconnecting lines and leads.
The first and second groups of semiconductor circuit elements may be mutually interspersed to form a substantially linear array.
In one interconnection scheme, the second conductive paths include a shared interconnecting line extending parallel to the array, and interconnecting leads electrically connecting the shared interconnecting line to the electrodes of the second group of semiconductor circuit elements. The first conductive paths include individual electrodes positioned between these interconnecting leads, individual interconnecting lines connecting the individual electrodes to the electrodes of the first group of semiconductor circuit elements, and a shared electrode extending parallel to the shared interconnecting line, electrically coupled to the first interconnecting pad, and electrically coupled to the individual electrodes through the semiconductor layer beneath the shared interconnecting line.
In another interconnection scheme, the second conductive paths include a branched interconnecting line extending generally parallel to the substantially linear array, with branches leading to the electrodes of the second group of semiconductor circuit elements. The first conductive paths include one or more electrode pads disposed between respective pairs of branches of the branched interconnecting line, electrically coupled to the first interconnecting pad through the semiconductor layer, and interconnecting leads connecting these electrode pads to the electrodes of the second group of semiconductor circuit elements. The first interconnecting pad may be seated on one of the electrode pads.
The substantially linear array may be staggered, the first and second groups of semiconductor circuit elements being offset in mutually opposite directions. The two groups of semiconductor circuit elements may be separated by a trench. Each semiconductor circuit element may be disposed in a separate part of the semiconductor layer.
A plurality of third interconnecting pads may be disposed on the dielectric film on the opposite side of the array from the first and second interconnecting pads, each third interconnecting pad being electrically coupled to a mutually adjacent pair of the semiconductor circuit elements, one belonging to the first group, the other belonging to the second group.
The semiconductor layer may include a gallium arsenide (GaAs) contact layer, aluminum gallium arsenide (AlGaAs) cladding layers, and an AlGaAs active layer. The semiconductor circuit elements may be light-emitting elements.
The invention also provides an optical printing head including at least one semiconductor array device of the invented type, and an electrophotographic printer including at least one such optical printing head.


REFERENCES:
patent: 6356448 (2002-03-01), DiBene et al.
patent: 2001-77431 (2001-03-01), None

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