Fishing – trapping – and vermin destroying
Patent
1992-05-18
1993-12-07
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
257 69, 257204, H01L 2170
Patent
active
052683230
ABSTRACT:
A semiconductor array in a CMOS technology is described in which the gate electrodes are of p.sup.+ -doped polysilicon in the case of p-channel transistors and of n.sup.+ -doped polysilicon in the case of n-channel transistors. If the gate electrodes of two complementary transistors are connected at the gate level, a polysilicon diode is created at the connection point. In accordance with the invention, the polysilicon diode is short-circuited with a polysilicide layer. A method is described for short-circuiting this polysilicon diode without additional masking steps using a metal silicide layer. In a further embodiment of the invention, the silicide is restricted to the area of the polysilicon diode. In addition, a method is described using which the polysilicon diodes can be short-circuited in a self-adjusting polysilicide process.
REFERENCES:
patent: 4703552 (1987-11-01), Baldi et al.
patent: 4804636 (1989-02-01), Groover, III et al.
patent: 4890141 (1989-12-01), Tang et al.
patent: 5010032 (1991-04-01), Tang et al.
patent: 5190886 (1993-03-01), Asahina
IBM Technical Disclosure Bulletin, vol. 32, No. 3B, Aug., 1989, "CMOS Processes With Low Resistance p- And n-Doped Gates".
Fischer Gerhard
Plagge Walter
Chaudhuri Olik
Eurosil Electronic GmbH
Pham Long
LandOfFree
Semiconductor array and method for its manufacture does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor array and method for its manufacture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor array and method for its manufacture will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2015532