Semiconductor arrangement preventing damage during contact...

Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...

Reexamination Certificate

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C257S797000

Reexamination Certificate

active

06188124

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to a semiconductor arrangement and, more specifically, to a semiconductor arrangement that limits damage caused by mask contact processing of the semiconductor arrangement.
BACKGROUND OF THE INVENTION
Masks are conventionally used to form desired films, layers, structures, and the like during the processing of a semiconductor arrangement. As illustrated in
FIG. 1
, a conventional two-level semiconductor arrangement
1
includes a semiconductor substrate
10
. A first active region
18
, a dielectric layer
20
, and a second active region
28
are disposed on or over semiconductor substrate
10
. In forming the second active region
28
, a mask
30
, as illustrated in
FIG. 2
, is applied to the dielectric layer
20
. Application of mask
30
on dielectric layer
20
occurs at the highest point
21
of the surface of the dielectric layer
20
underlying mask
30
.
Physical contact between mask
30
and the dielectric layer
20
at the highest point
21
risks damage to the dielectric layer
20
, such as by scratching the dielectric layer
20
. Damage to the dielectric layer
20
has not been a problem for conventional semiconductor arrangements, such as that illustrated in
FIG. 1
, because mask
30
contacts the dielectric layer
20
at an inactive surface portion
23
of the dielectric layer
20
, which is an area that will be free of active semiconductor circuitry. The second active region
28
will ultimately reside on an active portion
24
of the dielectric layer
20
, which is not contacted by the mask
30
. Damage to the inactive surface portion
23
of the dielectric layer
20
can be removed without great difficulty by subsequent processing, such as by dicing. Alternatively, in some semiconductor arrangements, damage to the inactive surface portion
23
of the dielectric layer
20
can be ignored without affecting performance.
Recently, the increased demand for larger active portions
24
has led to the positioning of active regions closer to the edge of the semiconductor arrangement. This configuration more fully utilizes the substrate real estate. Such an arrangement is illustrated in FIG.
3
: the second active region
28
is closer to the edge
25
of the dielectric layer
20
in the semiconductor arrangement of
FIG. 3
than it is in the semiconductor arrangement of FIG.
1
.
In forming second active region
28
, mask
30
is again applied to the semiconductor arrangement
1
, as illustrated in FIG.
4
. The mask
30
causes damage to the active portion
24
of the dielectric layer
20
, however, where the second active region
28
will ultimately reside. Unfortunately, this damage cannot be ignored because it affects formation of the second active region
28
, thereby affecting performance of the semiconductor chip. Although further processing can repair defects of the damaged second active region
28
, such repair processing incurs additional time and expense and is therefore undesirable.
The deficiencies of the processing of conventional semiconductor arrangements show that a need exists for a new semiconductor arrangement which limits damage caused by physical contact between a mask and a portion of the dielectric layer that will ultimately comprise a second active region.
SUMMARY OF THE INVENTION
To overcome the shortcomings of conventional semiconductor arrangements, a new semiconductor arrangement and process of fabrication are provided. An object of the present invention is to provide a semiconductor arrangement that reduces physical contact between a mask and active portions of the dielectric layer. A related object is to reduce damage to the active portions otherwise caused by physical contact of the mask during processing of the semiconductor arrangement.
To achieve these and other objects, and in view of its purposes, the present invention provides a semiconductor arrangement and process of fabrication. The semiconductor arrangement of the present invention comprises a substrate having disposed on a top surface a first active region and a dummy region. The first active region. Formed on the top surface of the substrate, over the dummy region and the first active region, is a dielectric layer. The surface of the dielectric layer has an inactive portion and an active portion. A mask is applied to the dielectric layer such that the mask contacts the inactive portion and does not contact the active portion.
The present invention also provides a process of fabricating a semiconductor arrangement. First, a first active region and a dummy region are formed on a top surface of a substrate. The first active region and dummy region are formed such that the first active region and the dummy region are spaced from one another without any contact, and the dummy region is closer to an edge of the surface of the substrate in comparison to the first active region. Next, a dielectric layer is formed on the first active region, the dummy region, and a portion of the surface of the substrate which is not covered by the first active region and the dummy region. The dielectric layer has a surface having an inactive portion and an active portion. Next, a mask is applied to the dielectric layer such that the mask contacts the inactive portion and does not contact the active portion.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.


REFERENCES:
patent: 3951701 (1976-04-01), Csillag
patent: 4194233 (1980-03-01), Jones et al.
patent: 5430325 (1995-07-01), Sawada et al.
patent: 5763936 (1998-06-01), Yamaha et al.
patent: 6066883 (2000-05-01), Hosier et al.
Sorab K. Ghandhi, VLSI Fabrication Principles Silicon and Gallium Arsenide, Second Edition, pp. 674-675 (1994).
Stanley Wolf, Richard N. Tauber, Silicon Processing for the VLSI Era, vol. 1, pp. 430-432.

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