Semiconductor arrangement, particularly a storage arrangement wi

Communications: electrical – Digital comparator systems

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307238, 307279, G11C 1140

Patent

active

039757188

ABSTRACT:
A storage arrangement employing first and second field effect transistors which are complementary to one another and connected in series, with the second transistor being of the depletion type, a load element, such as a resistor or transistor, being connected in series with such first mentioned transistors, with one side of such load element connected to the drain terminal of the first transistor and the other side of such load element connected to a line to which a supply voltage is connected, the drain-terminal of the second transistor being connected to a second line, which may form a word line, the gate terminal of the second transistor being connected to the drain terminal of the first transistor, and, preferably, a selector element such as a diode or transistor being operatively disposed between a third line and the junction of the load element and drain terminal of said first transistor, which third line may form a bit line, and a method of operating such arrangement.

REFERENCES:
patent: 3753248 (1973-08-01), Lynes et al.

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