Semiconductor arrangement and method for its manufacture

Details Semiconductor arrangement and method for its manufacture Semiconductor arrangement and method for its manufacture

1994-06-23

1996-07-30

Wojciechowicz, Edward

Fishing, trapping, and vermin destroying

437 81, 437158, 437235, 437245, 257603, 257605, H01L 21302, H01L 29861

Patent

active

055411401

ABSTRACT:
Semiconductor arrangements, in particular diodes, have a p-layer and two n-layers that are doped to varying degrees of thickness. The p-n junction between the p-layer and the heavily doped n-layer is arranged in the chip so as to allow it to lie completely inside the chip. The p-n junction between the p-layer and the n-layer is situated in the outside areas of the chip. This arrangement does not permit any high field strengths to occur on the outside of the chip and, at the same time, it makes it possible for easily reproducible properties to be achieved. The manufacturing method can also be carried-out outside of a clean room.

REFERENCES:
patent: 3264149 (1966-08-01), Batdoff

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