Data processing: artificial intelligence – Neural network – Structure
Reexamination Certificate
1998-03-13
2001-12-25
Davis, George B. (Department: 2122)
Data processing: artificial intelligence
Neural network
Structure
C326S098000, C326S119000, C327S389000
Reexamination Certificate
active
06334120
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor arithmetic circuit and data processing device, and more particularly relates to a highly functional semiconductor integrated circuit and data processing device capable of executing size comparisons of a plurality of inputted data at high speed in a time-continuous manner using hardware.
2. Description of the Related Art
In the fields of data processing and automatic control, the comparison of data expressed in numerical values and determinations as to the relative size thereof serve an extremely important function.
For example, examples thereof include the selection of the larger of two numbers, the extraction of data having a maximum value among a plurality of inputted data, and so-called sorting, in which a plurality of data are arranged by size of the numerical values thereof.
Such operations are normally conducted by using calculators; however, because a large number of operations are required, time is required and the use thereof in real-time control is extremely difficult. In particular, in the case of use in the control of robots and the like, calculations must be carried out by equipment attached to the robots, so that realization using small LSI chips is desired.
However, when attempts are made to conduct such processing via the programming of microprocessors, an extremely large amount of time is required, and practical application is essentially impossible. For this reason, research and development has been conducted into the production of a circuit which is capable of directly conducting size comparisons using hardware; however, a large number of elements are required in order to realize such a circuit, and operations must be conducted through a number of stages, so that small-scale LSI which is capable of high speed operations has not been realized.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor device which is capable of conducting size comparison operations with respect to a plurality of real time data at high speed, using simple circuitry.
The semiconductor arithmetic circuit comprises a semiconductor arithmetic circuit which is constructed using one or more neuron MOS transistors provided with a semiconductor region of one conductivity type on a substrate, source and drain regions of an opposite conductivity type provided within this region, and a floating gate electrode which is provided at a region separating the source and drain regions via an insulating film in an electrically floating state. A plurality of input gate electrodes which are capacitively coupled with the floating gate electrode via insulating films is also included. An inverter circuit group comprising a plurality of inverter circuits constructed using neuron MOS transistors is provided, and an externally supplied predetermined signal voltage is applied to at least one first input gate of the input circuits, and the output signals of all of the inverters contained in the inverter circuit group, or output signals obtained by passing these output signals through a predetermined number of stages of inverter circuits, are inputted into a first logical arithmetic circuit and a second logical arithmetic circuit, and the output signal of the first logical arithmetic circuit, or an output signal obtained by passing this through a predetermined number of stages of inverter circuits, is inputted into a third logical arithmetic circuit which is controlled by the output signal of the second logical arithmetic circuit, and the output of the third logical arithmetic circuit is fed back to the second input gates of the inverter circuits contained in the inverter circuit group, and as a result of the output signals of the inverter circuit group, the position having a maximum voltage among the signal voltages inputted into the inverter circuit group is specified.
The first logical arithmetic circuit has the function of outputting a predetermined logical signal to the output terminal thereof when the number of values of ‘1’ or ‘0’ among the plurality of binary signal inputs exceeds the predetermined number.
Furthermore, the first logical arithmetic circuit contains an inverter circuit constructed using one or more neuron MOS transistors.
The first logical arithmetic circuit outputs a value of ‘0’ when the number of values of ‘1’ among the plurality of binary signal inputs is one or more.
The second logical arithmetic circuit alters its output signal in accordance with predetermined rules when the number of values of ‘1’ or ‘0’ among the plurality of binary inputs exceeds a predetermined number. Furthermore, the second logical arithmetic circuit has the function of specifying the number of values ‘1’ among the plurality of binary signal inputs, and alters the output signal thereof in accordance with predetermined rules in accordance with the number of values of ‘1’.
The third logical arithmetic circuit attenuates or amplifies, by a predetermined proportion, an inputted signal by means of at least one control signal, and outputs this signal. Alternatively, a predetermined signal voltage, or the input signal, may be used as the output signal. Alternatively, the third logical circuit may have two or more outputs, and the outputs of the third logical arithmetic circuit may be inputted into an identical number of second input gates.
The data processing device of the present invention is provided with semiconductor arithmetic circuits, a plurality of which are connected in stages, and which are provided with a mechanism for accepting a plurality of numerical values from the exterior, and storing these, and in which the plurality of numerical values are inputted into a semiconductor arithmetic circuit, the output signal of the semiconductor arithmetic circuit is inputted into a fourth logical arithmetic circuit, and by means of the output signal of the fourth logical arithmetic circuit, at least one numerical value is selected from the plurality of numerical values and outputted.
The semiconductor circuits which are connected in a plurality of stages individually select and execute optimal processing in accordance with the plurality of numerical values applied thereto.
Furthermore, a fifth logical arithmetic circuit is provided which receives predetermined signals from both the sending side semiconductor system and the receiving side semiconductor system of the numerical value selected, and when these signals meet prespecified conditions, outputs predetermined signals to both sides.
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Morimoto Tatsuo
Ohmi Tadahiro
Shibata Tadashi
Davis George B.
Knuth Randall J.
Shibata Tadashi
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