Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With large area flexible electrodes in press contact with...
Reexamination Certificate
2000-06-09
2002-04-16
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With large area flexible electrodes in press contact with...
C257S181000, C257S723000
Reexamination Certificate
active
06373129
ABSTRACT:
BACKGROUND OF THE INVENTION AND RELATED ART STATEMENT
The present invention relates to a semiconductor apparatus including a plurality of power devices, such as insulated gate bipolar transistors (IGBTs). More specifically, the present invention relates to a semiconductor apparatus of a pressure contact type including a flat package that incorporates a plurality of semiconductor chips, each including a first main electrode (emitter) and a control electrode (gate) on a first major surface thereof, and a second main electrode (collector) on a second major surface thereof.
IGBTs are used widely as power switching devices in an inverter for controlling the speed of a motor. Recently, applications of the IGBT are extended to the high capacity area where gate turn-off (GTO) thyristors have been used conventionally, since the IGBT is of voltage-drive-type to be easily used, and the safe working area of the IGBT is wide.
In manufacturing metal oxide semiconductor (MOS) control devices, such as IGBTs, the precision from several microns to submicrons is required, different in manufacturing the conventional GTO thyristors. Thus, the manufacturing process of forming a plurality of MOS control devices on one single wide wafer is not employable for obtaining a high throughput. In manufacturing a high-capacity semiconductor apparatus including a plurality of MOS control devices, it is necessary to mount a plurality of MOS device chips, each having 10 mm×10 mm to 28 mm×28 mm in area, in parallel to each other on a package.
In the MOS control device such as an IGBT, an emitter electrode and a gate electrode are formed side by side on a major surface of the semiconductor chip. Due to this configuration, in a general semiconductor module including a plurality of IGBTs incorporated in a package, current paths are formed by mounting the collectors formed on bottom surfaces of the IGBT chips on a metal base plate and by individually connecting the emitter electrodes and the gate electrodes to lead-out terminals with aluminum bonding wires. The metal base plate works also as a radiator for radiating heat generated in the IGBTs. The package including the IGBT chips incorporated therein is covered with a plastic casing and sealed with a resin, such as silicone gel.
In flat IGBTs of a pressure contact type for use in high electric power, a perfect air-tight structure, that covers the IGBT package with a ceramic casing and seals nitrogen gas in the ceramic casing, is employed. Metal electrodes of molybdenum and the like are pressed to contact the collector electrodes and the emitter electrodes of the IGBT chips for forming current paths and for radiating heat generated in the IGBT chips.
The semiconductor apparatus disclosed in Japanese Unexamined Patent Publication (KOKAI) No. H07-94673 uses aluminum bonding wires for the connection of the gates of the IGBT chips, since any current does not flow through the gates even when a bias voltage is applied thereto.
Japanese Unexamined Patent Publication (KOKAI) No. H11-97462 discloses another method for gate wiring that uses a contact probe. The chip-side end face of the contact probe is provided with a spring function and a lead wire is connected to the other end face of the contact probe. A general wire wound resistor is connected to the lead wire. Finally, a plurality of lead wires from the wire wound resistors is bunched to form a gate terminal for the flat IGBT package. A plurality of such contact probes is fixed to a resin frame that positions a plurality of the IGBT chips.
Recently, the flat IGBT of the pressure contact type has been used more widely and the capacity thereof has been increasing. As the applications of the flat IGBT of the pressure contact type and the capacity thereof increase, it is required for the flat IGBT of the pressure contact type to exhibit an improved reliability and an improved breakdown voltage.
However, the semiconductor apparatus, that uses aluminum bonding wires for the gate wiring, is not suitable for increasing the breakdown voltage. More in detail, there is no problem for the breakdown voltage up to around 2500 V. However, when the voltage of more than 4000 V is applied, an electric field localizes to the fine bonding wires of 300 &mgr;m in diameter and discharge occurs between the collector and the portion of the bonding wires, to which the electric field is localized.
In the semiconductor apparatus that uses the conventional contact probe, the lead wires are led out from the resin frame, to which the contact probes are fixed, and the led out lead wires are bunched to form a gate terminal. Thus, the gate wiring is very complicated, and if a number of chips is increased to increase the current capacity, it can not house the IGBT chips in one package. As the constituent elements increase, the reliability of the semiconductor apparatus is decreased.
With increasing the current capacity of the flat IGBT package, the number of the IGBT chips in the package increases. If many contact probes are arranged on a resin frame, it impairs the precise positioning of the contact probes on the gate pads of the IGBT chips and causes dislocation between the constituent elements by cyclic temperature changes due to the differences between the thermal expansion coefficients of the constituent elements.
In view of the foregoing, it is an object of the invention to provide a semiconductor apparatus of a pressure contact type, including a flat package incorporating a plurality of MOS devices such as IGBTS, which facilitates to reduce a number of constituent elements and improve precise positioning of the constituent elements.
It is another object of the invention to provide a semiconductor apparatus of the pressure contact type, which facilitates to improve the breakdown voltage, current capacity and reliability thereof.
SUMMARY OF THE INVENTION
According to the invention, there is provided a semiconductor apparatus of a pressure contact type constituting a flat package, including a plurality of semiconductor chips, each having a first major surface, a second major surface, a first main electrode on the first major surface, a control electrode on the first major surface, and a second main electrode on the second major surface. The semiconductor apparatus includes a control base plate having an opening formed at a position corresponding to the first major electrodes of the semiconductor chips and electrically conductive sections formed at positions facing the control electrodes of the semiconductor chips, and pressure contact electrodes. Each pressure contact electrode has two distal contact ends, and is arranged between corresponding one of the control electrodes of the semiconductor chips and corresponding one of the electrically conductive sections of the control base plate. One of the distal contact ends thereof contacts the corresponding one of the control electrodes, and the other of the distal contact ends contacts the corresponding one of the electrically conductive sections of the control base plate. The pressure contact electrodes transmit a control signal from the control base plate to the semiconductor chips.
The semiconductor apparatus according to the invention connects the common control base plate and the control electrodes of the semiconductor chips with the pressure contact electrodes, each having two distal contact ends. The pressure contact electrode, which is thicker than the lead wire, prevents discharge between the collector electrode and the pressure contact electrode, and facilitates to improve the breakdown voltage. Since the constituent elements for gate wiring are the pressure contact electrodes arranged corresponding to the control electrodes of the semiconductor chips and the common control base plate common to the package, the number of the constituent elements is greatly reduced, the failure rate is suppressed to the minimum level and the package size is reduced.
REFERENCES:
patent: 5610439 (1997-03-01), Hiyoshi et al.
patent: 5777351 (1998-07-01), Taguchi et al.
patent: 5990501 (1999-11-01), Hi
Takahashi Yoshikazu
Yamazaki Kazuaki
Cao Phat X.
Fuji Electric & Co., Ltd.
Kanesaka & Takeuchi
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