Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Smart card package
Reexamination Certificate
2001-05-15
2002-10-22
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Smart card package
C257S686000
Reexamination Certificate
active
06469373
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-141301, filed May 15, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor apparatus, and in particular, to a package having an under-fill resin sheet interposed between a wire substrate and a semiconductor chip.
A semiconductor apparatus is of such a type that has a semiconductor package in which a wiring substrate mounting a semiconductor chip is resin sealed with a mold resin.
FIG. 10
is a sectional view of a package (CSP: Chip Size (Scale) Package) of a flip chip connection type having a conventional structure.
As a wiring substrate, there is employed an interposer made of a polyimide film (insulation film). A wiring layer
105
such as Cu is provided on a surface of a polyimide film
100
. A chip
101
is disposed on the polyimide film
100
, and is flip-chip connected to the polyimide film
100
. That is, a connection electrode
106
that is formed on a lower face of the chip
101
, and is electrically connected to its inside circuit (not shown) is connected to a wiring layer
105
formed on the surface of the polyimide film
100
. An under-fill resin sheet
102
made of an epoxy resin or the like is provided between the chip
101
and the polyimide film
100
, and a space between them is sealed from the outside. A resin sealing body
104
made of a mold resin such as epoxy resin is provided all over the chip, and the entire chip is sealed from the outside. That is, the resin sealing body
104
made of a mold resin is provided on the chip
101
and on the filling resin sheet
102
, and the entire chip is sealed from the outside.
A laminate body made of the polyimide film
100
, under-fill resin sheet
102
, chip
101
, and resin sealing body
104
, that is, a package, is mounted on a mount substrate
107
. When the package is mounted on the mount package
107
, a wiring layer
105
formed on the surface of the polyimide film
100
is connected to a wiring layer
108
such as Cu formed on the surface of the mount substrate
107
via an external terminal
103
made of solder or the like provided at the periphery of the polyimide film
100
.
The chip
101
and under-fill resin sheet film
102
are substantially identical to each other in size, and the under-fill resin sheet
102
does not protrude from a side face of the chip
101
. The entire chip is sealed by the resin sealing body
104
made of a mold resin such as epoxy resin formed to be covered on the polyimide film
100
. The mount height of the package is 0.5 (Max), and the thickness of the chip
101
is about 0.2 mm.
FIG. 11
is a sectional view illustrating a state in which the package of the semiconductor apparatus shown in
FIG. 10
is mounted on the mount substrate
107
. A terminal
103
of the polyimide film
100
is connected to a wire
108
on the mount substrate
107
(FIG.
11
).
After the package of the semiconductor apparatus shown in
FIG. 10
has been mounted on the mount substrate
107
, a mount TCT (Temperature Cycling Test) test is carried out. When this test is carried out, a stress is experienced in the solder of the terminal
103
due to the difference in thermal expansion coefficients between the members, a crack occurs within the solder, finally resulting in electrical disconnection. In the package having a structure shown in
FIG. 10
, a solder portion is mainly disconnected in a comparatively small number of test cycles because the Young's modulus of mold resin is particularly high due to the difference in the thermal expansion coefficient between the mount substrate and the mold resin.
In addition, reliability tests for the semiconductor apparatus include a re-flow test for damping the package, thereby carrying out re-flow. This test is conducted to find out whether or not a reliability-error occurs in the package when re-flow is applied, due to water in the package contained when it is damped. In the package shown in
FIG. 10
, as shown in
FIG. 12
, there is no escape path through which water accumulated by the under-fill resin sheet
102
is effectively discharged to the outside during damping. Thus, when re-flow is applied, a crack occurs with the under-fill resin sheet
102
, and the re-flow resistance is lowered.
In addition, in a CSP package of flip chip type, as shown in
FIG. 13
, a mold resin of the resin sealing body
104
is loaded on the wiring layer
105
such as Cu formed on the polyimide film
100
. An adhesion between Cu and the mold resin is so lowered as to be prone to deterioration, thus causing their separation. In manufacture of the CSP package of flip chip type, the chip
101
is mounted after the under-fill resin sheet
102
has been pasted on a large polyimide film
100
, and then, the entirety is resin sealed with the mold resin
104
. Then, there is adopted a method for carrying out dicing cut into individual pieces in units of chip
101
. When cut into individual pieces, a separation occurs between Cu and the mold resin.
FIG.
14
A and
FIG. 14B
, FIG.
15
A and
FIG. 15B
, FIG.
16
A and
FIG. 16B
, and FIG.
17
A and
FIG. 17B
are plan views and sectional views of laminate structures in manufacturing processes, for illustrating a conventional manufacturing method comprising the steps of: forming a laminate body of the polyimide film
100
, under-fill resin sheet
102
, chip
101
, and mold resin
104
, and cutting the formed laminate body along a package region, thereby forming a plurality of semiconductor apparatuses.
FIG. 14B
,
FIG. 15B
,
FIG. 16B
, and
FIG. 17B
are sectional views of one package region.
As a wiring substrate, there is employed an interposer made of the polyimide film
100
. A package region is partitioned in plurality on the wiring substrate
100
having the polyimide film
100
provided on the surface (FIG.
14
A). Each package region is a unit region in which one chip is mounted. Each of the under-fill resin sheets
102
is mounted on each package region of the polyimide film
100
(FIG.
14
B). Next, one chip
101
is disposed on each under-fill resin sheet
102
, and is pasted by thermal pressure welding (FIG.
15
A). Next, the entirety of the polyimide film
100
is covered with the mold resin
104
(FIG.
15
B). Then, a laminate body of the polyimide film
100
, under-fill resin sheet
102
, chip
101
, and mold resin
104
is cut into individual pieces along individual package regions, thereby forming a plurality of semiconductor apparatuses shown in FIG.
10
.
BRIEF SUMMARY OF THE INVENTION
The present invention has been made in view of such circumstances. It is an object of the present invention to provide a semiconductor apparatus having a chip mounted on a wiring substrate via an under-fill resin sheet, the semiconductor apparatus being resin sealed with a resin sealing body, wherein a stress applied to a solder terminal formed on the wiring substrate is reduced. It is another object of the present invention to improve the re-flow resistance and prevent a wire from separating from a resin sealing body by effectively exhausting water contained in an under-fill resin sheet to be used.
A semiconductor apparatus of the present invention includes a chip mounted on a wiring substrate via an under-fill resin sheet, the semiconductor apparatus being resin sealed with a resin sealing body, wherein the under-fill resin sheet is greater than the chip size, and its end is exposed from at least one side face of the resin sealing body. Since an end of the under-fill resin sheet is exposed from at least one side face of the resin sealing body, then the water contained in the under-fill resin sheet escapes from an exposed end of the under-fill resin sheet to the outside of the resin sealing body, thus making it possible to improve re-flow resistance of the semiconductor apparatus. When this under-fill resin sheet is substantially identical to the resin sealing body in size, the end
Funakura Hiroshi
Hosomi Eiichi
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Nelms David
Nguyen Thinh
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