Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2002-11-27
2004-07-20
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S066000, C257S072000, C257S448000, C257S536000, C438S166000, C438S404000, C438S592000
Reexamination Certificate
active
06765281
ABSTRACT:
BACKGROUND
1. Field
This patent specification describes a semiconductor apparatus and method of making the same, and more particularly a semiconductor apparatus with a stable contact resistance and a method of making the semiconductor apparatus.
2. Discussion of The Background
A highly integrated SRAM (static random access memory) and a hybrid LSI (large-scale integration) circuit with an analog circuit, typically use a relatively high resistive element made of a polysilicon film.
A resistive value of a resistive element is generally expressed by an equation;
R
=(&rgr;/
t
)×(
L/W
),
wherein R represents a resistive value, &rgr; represents a resistivity, t represents a film thickness, L represents a length of the resistive element, and W represents a width of the resistive element.
From the above equation, it is understood that an increase of one or both of the resistivity &rgr; and the length L or a decrease of one or both of the film thickness t and the width W increases the resistive value R. A decrease of the film thickness t is useful as a method of stably increasing the resistive value R. However, it also causes problems such as those discussed below.
FIG. 1
is a schematic diagram showing a cross section view of a polysilicon thin film resistive element with a contact hole for connecting the thin film resistive element to a metal wiring. In
FIG. 1
, a resistive element pattern
41
is formed on a field oxide film
3
formed on a semiconductor substrate. The resistive element pattern
41
is made of a polysilicon film including an N-type or P-type impurity. On the resistive element pattern
41
, an inter-layer insulating film
43
is formed. To form a contact to the resistive element
41
, a relatively low resistive region
45
including a relatively high concentration impurity is normally formed to both sides of the resistive element pattern
41
to have a better electrical conductivity. A contact hole
47
is formed in the inter-layer insulating film
43
to the low-resistive region
45
. A metal wiring layer
49
is formed on the inter-layered film
43
. A conducting filler
51
fills in the contact hole
47
to electrically connect the low-resistive region
45
and the metal wiring layer
49
.
When the polysilicon film constituting the resistive element
41
and the low-resistive region
45
are made thin to increase a resistance value of the resistive element
41
, the low-resistive region
45
may unexpectedly be etched through by the dry etching used to form the contact hole
47
. As a result, the bottom of the contact hole
47
comes through the low-resistive region
45
and reaches the base, the field oxide film
3
, as shown in FIG.
2
. In this case, a contact area between the conducting filler
51
filled in the contact hole
47
and the low-resistive region
45
is limited to a side portion
47
a
of the contact hole
47
and a contact resistance consequently increases. As a result, an attempt to make a desired resistive value by determining the length and width of the resistive element
41
fails and such a desired resistive value is not obtained.
One attempt to solve the above-mentioned problem is to make thicker the polysilicon film in the region forming the contact hole. This attempt is described, for example, in Japanese Laid-Open Patent Application Publication No. 05-055520, Japanese Laid-Open Patent Application Publication No. 06-069207, Japanese Laid-Open Patent Application Publication No. 10-032246, and Japanese Laid-Open Patent Application Publication No. 10-163430.
For example, a first background method described in Japanese Laid-Open Patent Application Publication No. 05-055520 is shown in FIG.
3
. This method forms a thick polysilicon film
155
for a low-resistant portion on a first insulating film
103
(i.e., the field oxide film
3
). The polysilicon film
155
includes an additive of a high concentration impurity to make an electrical connection in a wiring region via a metal wiring layer
149
and a contact portion
147
(i.e., similar in function to contact hole
47
) for an electrode. After that, the polysilicon film
155
is etched to have an opening
153
for a high-resistive portion, reaching the first insulating film
103
. Then, a thin polysilicon film
141
(i.e., similar in function to resistive element pattern
41
) is formed to cover the entire surfaces of the first insulating film
103
including the opening
153
and the polysilicon film
155
. The thin polysilicon film
141
is for a high-resistive portion and includes no impurity additives or a relatively low concentration impurity additive. After that, a second insulating film
143
(i.e., the inter-layer insulating film
43
) is formed on the entire surface of the thin polysilicon film
141
and, in the second insulating film
143
, the contact portion
147
for an electrode is formed.
In this way, the first background method attempts to avoid variations of the value of contact resistance by having the polysilicon film
155
underneath the contact portion
147
which may include a contact opening portion
157
coming through the thin polysilicon film
141
that constitutes a resistive element.
When the first background method is applied to a manufacturing process for a SRAM (static random access memory) or a hybrid LSI (large scale integration) circuit, for example, it is needed to form a polysilicon-made gate electrode for a MOS (metal oxide semiconductor) transistor in addition to the resistive element pattern which is the thin polysilicon film
141
. This patent specification uses the term MOS for FET (field effect transistors) using a gate made of any conductive material such as a metal, a polysilicon, etc. When an electrode of the MOS transistor is formed with the thick polysilicon film
155
, a residue film may be formed from the thin polysilicon film
141
on the side of the polysilicon electrode made from the thick polysilicon film
155
. Such residue film on the electrically conductive film can significantly affect the characteristic of the transistor. To avoid the generation of such residue, the process may become excessively complex.
A second background method is described in Japanese Laid-Open Patent Application Publication No. 06-069207, and its procedure is shown in
FIGS. 4 and 5
. As shown in
FIG. 4
, a first polycrystalline silicon layer
255
(i.e., similar in function to thick polysilicon film
155
) is formed on the insulating film
3
formed on the semiconductor substrate
1
. The upper surface of the first polycrystalline silicon layer
255
is covered with a silicon dioxide film
259
serving as an insulating film, and a second polycrystalline silicon layer
241
(i.e., similar in function to resistive element pattern
41
) is formed on the silicon dioxide
259
and the insulating film
3
of the substrate surface such that the second polycrystalline silicon layer
241
contacts by its side the silicon dioxide
259
and the insulating film
3
.
With this arrangement, a multi-layered structure of the first and second polycrystalline silicon layers
255
and
241
is applied to the region of the wiring and the contact holes, and only the second polycrystalline silicon layer
241
is applied to the high resistive region. Therefore, as in the case of the first background method, the contact resistive value would not be affected by the second polycrystalline silicon layer
241
even if the second polycrystalline silicon layer
241
comes through around the contact opening area because there is the first polycrystalline silicon layer
255
underneath the second polycrystalline silicon layer
241
.
As shown in
FIG. 5
, the second background method forms a gate insulating film
261
on the semiconductor substrate
1
as it forms the resistive element. Then, the first polycrystalline silicon layer
255
and the silicon dioxide film
259
are formed on the gate insulating film
261
. After that, the second polycrystalline silicon layer
241
is formed to cover the first polycrystalline silicon layer
255
and the silicon dioxide film
259
. Th
Cooper & Dunham LLP
Nelms David
Nguyen Dao H.
Ricoh & Company, Ltd.
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