Fishing – trapping – and vermin destroying
Patent
1994-10-26
1997-01-07
Fourson, George
Fishing, trapping, and vermin destroying
437 31, 437 57, H01L 21265, H01L 2170, H01L 2700
Patent
active
055916570
ABSTRACT:
The invention increases withstand voltage and current capacity of a DMOS portion simultaneously built in by the BiCMOS process. The manufacturing method for the DMOS portion is comprised of steps of forming an ion-implanted layer in a surface of a P-type well; forming a gate electrode; self-aligning a P-type base region by employing the P-type base formation process of the bipolar transistor and by using the gate electrode as a mask; forming a side wall on a side face of the gate electrode by employing the process for forming the LDD structure of the CMOS; and self-aligning an N+type source region by employing the process for forming the N+type source and the drain of the CMOS and by using the side wall as a mask. The effective channel length becomes longer by the side wall length and the rate of heavily doped channel portion to the total channel length becomes high. The manufacturing method effectively suppresses surface punch through by the high rate of the heavily doped channel portion and facilitates increasing withstand voltage and current capacity of the DMOS portion even when the total acceptor amount in the ion-implanted layer is insufficient.
REFERENCES:
patent: 4104784 (1978-08-01), Klein
patent: 4217688 (1980-08-01), Ipri
patent: 4503598 (1985-03-01), Vora et al.
patent: 4716126 (1987-12-01), Cogan
patent: 4967244 (1990-10-01), Bauer
patent: 5072267 (1991-12-01), Hattori
IEEE IEDM 88, pp. 796-799 (1988), Dolny et al. "Complementary DMOS/BiCMOS technology for power IC applications".
IEEE J. Solid-State Circuit, vol. SC-16, pp. 212-226, Jun. 1981.
Proceedings of 1992 International Symposium on Power Semiconductor Devices & ICs, Tokyo, pp. 52-57.
Fujishima Naoto
Kitamura Akio
Nagayasu Yoshihiko
Dutton Brian K.
Fourson George
Fuji Electric & Co., Ltd.
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