Semiconductor apparatus including semiconductor chip with...

Details Semiconductor apparatus including semiconductor chip with... Semiconductor apparatus including semiconductor chip with...

2011-06-07

2011-06-07

Smoot, Stephen W (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S778000, C257S781000, C257SE23021

Reexamination Certificate

active

07956461

ABSTRACT:
In order to solve a problem of occurrence of delamination of interlayer film due to occurrence of a crack in an LSI wiring layer in a UBM lower layer immediately under a solder bump in an outer periphery of an LSI chip, a semiconductor apparatus of the present invention includes a stress boundary between compressive stress and tensile stress in an LSI wiring layer of a bump lower layer and in order to alleviate the stress present in the bump lower layer tensile stress material is arranged on a compressive stress side or compressive stress material is arranged on a tensile stress side with a stress boundary of the LSI wiring layer as a boundary.

REFERENCES:
patent: 6313537 (2001-11-01), Lee et al.
patent: 7297572 (2007-11-01), Salmon
patent: 11-186320 (1999-07-01), None
patent: 2000-340569 (2000-12-01), None
patent: WO 2007/064073 (2007-06-01), None

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