Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Encapsulating
Reexamination Certificate
2000-11-17
2003-04-15
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Encapsulating
C438S112000, C438S124000, C438S126000, C438S977000, C257S686000, C257S787000
Reexamination Certificate
active
06548330
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a new semiconductor apparatus and a method of fabricating a semiconductor apparatus. More in details, the present invention relates to a technology capable of arbitrarily designing an interconnection shape of a surface layer to thereby promote reliability of connection in laminating layers and making destruction of a semiconductor element difficult to cause in a semiconductor apparatus having interconnections for connecting laminated layers on a surface and a back of a substrate and capable of laminating layers in multiple stages.
2. Description of the Related Art
In recent years, in addition to an increase in a necessary amount of a semiconductor memory dealt with by electronic apparatus, downsizing of electronic apparatus has been progressed and accordingly, it has been desired to mount a semiconductor memory having a large capacity by mounting area and volume which are made as small as possible.
Hence, there have been proposed various methods of constituting large capacity formation by using a plurality of pieces of semiconductor memories.
First, there is provided a constitution of laminating a plurality of pieces of semiconductor memories which have already been fabricated as semiconductor packages. However, since a thickness of the semiconductor package per se is thick and accordingly, when the semiconductor packages are laminated in multiple stages, there poses a problem in which a thickness of a total thereof becomes considerably thickened.
Further, there also has been proposed a structure of thinning the thickness by using a TAB tape. However, there poses a problem in which the TAB tape is generally expensive and is difficult to deal with.
Further, there also has been carried out a trial of thinning a thickness of a semiconductor element to be mounted. However, there poses a serious problem in view of dealing therewith such as crack of a wafer in transportation or a serious problem in view of inspection and integration thereof.
Hence, in order to realize a semiconductor memory package which is as thin as possible, it is effective to thin a semiconductor element after mounting the semiconductor element on a carrier such as a substrate. There are disclosed, in Japanese Patent Laid-Open No. 236694/1996, examples of semiconductor memories in each of which a total thickness in laminating layers in multiple stages is restrained to be thin by constituting the semiconductor memory in this way. These examples are shown in
FIGS. 13A
,
13
B,
13
C,
13
D and
13
E and
FIGS. 14A
,
14
B,
14
C and
14
D.
According to the example shown in
FIGS. 13A
,
13
B,
13
C,
13
D and
13
E, there is used a substrate ‘a’ constituted by electrically connecting a conductor pattern formed on a surface of the substrate ‘a’ and an inner bonding pad formed on a back of the substrate ‘a’ by a through hole formed at an inner portion or at an end face of the substrate ‘a’. A semiconductor element ‘b’ is mounted on the surface of the substrate ‘a’ (refer to
FIG. 13
A). Synthetic resin ‘c’ is injected between the substrate ‘a’ and the semiconductor element ‘b’ to thereby seal therebetween (refer to
FIG. 13
B). The semiconductor element ‘b’ is polished and ground to a desired thickness (refer to
FIG. 13
C). One unit ‘e’ is formed by forming bumps ‘d’ for laminating layers in multiple stages (refer to
FIG. 13
D). By laminating such units ‘e’ in multiple stages, a memory module ‘f’ having a large capacity is formed (refer to
FIG. 13
E).
According to the example shown in
FIGS. 14A
,
14
B,
14
C and
14
D, a cavity portion ‘g’ is provided, further, a substrate ‘i’ having end face through holes ‘h’ is used. First, a semiconductor element ‘j’ is mounted at inside of the cavity portion ‘g’ (refer to
FIG. 14
A). Synthetic resin ‘k’ is injected between the substrate ‘i’ and the semiconductor element ‘j’ to thereby seal therebetween (refer to
FIG. 14
B) A total including the semiconductor element ‘j’ is polished and ground to a desired thickness to thereby form on e unit ‘l’ (refer to
FIG. 14
C). By laminating such units ‘l’ in multiple stages and connecting the units ‘l’ by the end face through holes ‘h’ a memory module ‘m’ having a large capacity is formed (refer to
FIG. 14
D).
According to th e above-described related examples, in grinding the semiconductor element from the back, it is difficult to leave interconnections formed on the surface of the substrate. Further, it is difficult to bond together the end face through holes ‘h’ of the substrates ‘i’ laminated in multiple stages as in the example shown in
FIGS. 14A
,
14
B,
14
C and
14
D and even when the end face through holes ‘h’ can be bonded, a sufficient bond strength is not be achieved.
Further, in polishing and grinding the semiconductor element ‘b’ or ‘j’ on the back, the back of the semiconductor element ‘b’ or ‘j’ is not protected and accordingly, stress of polishing and grinding is directly exerted to the semiconductor element ‘b’ or ‘j’ and there is a concern of causing chipping or chip crack at the semiconductor element ‘b’ or ‘j’.
SUMMARY OF THE INVENTION
Hence, it is the object of the present invention to be capable of arbitrarily designing an interconnection shape of a surface layer to thereby promote reliability of connection in laminating layers and making destruction of a semiconductor element difficult to cause in a semiconductor apparatus having interconnections for connecting laminated layers on a surface and a back of a substrate and capable of laminating layers in multiple stages.
In order to achieve the above-described object of the present invention, there is provided a semiconductor apparatus, wherein a semiconductor element is mounted in a recess portion formed at a surface of a substrate having interconnection patterns connected by a through hole on two of the surface and a back thereof with a front thereof disposed on a lower side, a semiconductor element is sealed in the recess portion by a synthetic resin, and a back of the semiconductor element and the interconnection on the front are disposed in a same plane.
Therefore, according to the semiconductor apparatus of the present invention, the interconnection pattern is formed on the front to dispose in a plane the same as that of the back of the semiconductor element and accordingly, the interconnection pattern on the front can be arbitrarily designed and reliability of connection in laminating layers is enhanced. Further, the semiconductor element is mounted by disposing the front to the lower side and accordingly, a thickness of a total can be thinned by grinding the back.
Further, in order to achieve the above-described object of the present invention, there is provided a method of fabricating a semiconductor apparatus comprising a step of mounting a semiconductor element by disposing the front on the lower side in a recess portion shallower than a thickness of the semiconductor element, the recess portion being formed in a surface of a substrate having interconnection patterns connected by a through hole on two of the surface and a back thereof in which a thickness of an interconnection on the surface is made thicker than a thickness of an interconnection on the back, a step of sealing the semiconductor element in the recess portion by a synthetic resin and a step of grinding the substrate and the semiconductor element up to the interconnection on the surface.
Therefore, according to the method of fabricating a semiconductor apparatus of the present invention, the semiconductor element is mounted by disposing the front on the lower side and accordingly, the thickness of the total can be thinned by grinding the thickness from the back. Further, the thickness of the interconnection on the front is made thicker than the thickness of the interconnection of the back and accordingly, when there causes a dispersion in a thickness of the substrate, even by grinding the interconnection such that the thickness of the total becomes the same, the interconnection can firmly
Kato Masuo
Murayama Toshihiro
Tatsuno Yasufumi
Depke Robert J.
Holland & Knight LLC
Picardat Kevin M.
Sony Corporation
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