Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout
Reexamination Certificate
2008-08-07
2010-11-16
Garber, Charles D (Department: 2812)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
With electrical circuit layout
C438S022000, C438S048000, C438S128000, C257SE21613, C257SE21645, C257SE21657, C365S189011, C365S189160
Reexamination Certificate
active
07833841
ABSTRACT:
The present invention is a method for manufacturing a semiconductor apparatus including a chip which is fabricated in large numbers on a wafer and has a plurality of information blocks. In the method, a unique information bit is written in a chip discrimination block of each chip within a shot, which is a segmented region of the wafer, by a fixed pattern method. In addition, an information bit uniquely given to each shot within the wafer is written by a mask shift method. Further, an information bit uniquely given to each wafer is written in a wafer discrimination block of the chip which is fabricated on the wafer by the mask shift method and mask combination method.
REFERENCES:
patent: 7295467 (2007-11-01), Katayama et al.
Kando Hidehiko
Sakama Isao
Brundidge & Stanger, P.C.
Garber Charles D
Hitachi , Ltd.
Lee Cheung
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