Semiconductor antifuse structure and method

Details Semiconductor antifuse structure and method Semiconductor antifuse structure and method

1989-08-24

1990-04-03

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437203, 437245, 437228, H01L 21283

Patent

active

049140558

ABSTRACT:
A method for forming an array of antifuse structures on a semiconductor substrate which previously has had CMOS devices fabricated thereupon up to first metallization. A fuse structure is formed as a sandwich by successively depositing a bottom layer of TiW, a layer of amorphous silicon, and a top layer of TiW. The amorphous silicon is formed in an antifuse via formed in a dielectric layer covering the bottom layer of TiW. First metallization is deposited and patterned over the top layer of TiW. An intermetal dielectric layer is formed over the fuse array and second metal conductors are formed thereupon. An alternative embodiment includes forming an oxide sidewall spacer around the periphery of an antifuse structure. Connection resistance to the bottom layer of TiW is lowered by using a number of vias between the second-metal conductors and the bottom layer of TiW in a row of an array of antifuse devices.

REFERENCES:
patent: 4240094 (1980-12-01), Mader
patent: 4585490 (1986-04-01), Raffel
patent: 4617723 (1986-10-01), Mukri
patent: 4751197 (1988-06-01), Wills

Affiliated with

Also associated with

Rating

Semiconductor antifuse structure and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor antifuse structure and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor antifuse structure and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1357422