Semiconductor and method of fabricating

Semiconductor device manufacturing: process – Repair or restoration

Reexamination Certificate

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Details

C438S184000, C438S304000, C438S596000

Reexamination Certificate

active

06391661

ABSTRACT:

TECHNICAL FIELD
The present invention is concerned with a semiconductor structure and method of fabricating. More particularly, the present invention is concerned with eliminating potential drop across a semiconductor wafer that typically occurs during processing. According to the present invention, a sacrificial or removable conductive strap is coupled to the semiconductor substrate and conductor where desired, for maintaining a common voltage between the conductor and substrate.
BACKGROUND OF INVENTION
In the manufacture of semiconductive devices, the steps of depositing layers and etching selected portions of layers which constitute the final chip in many cases employ ion beam and/or plasma processes. However, processes such as plasma deposition, plasma etching and ion implantation contribute to charging damage, leakage paths and/or gate oxide blow out. In particular, during plasma processes, the semiconductor wafer surface becomes negatively charged causing a potential drop across the wafer because the surface which the wafer rests on is at a different potential than the plasma potential. Typically, electrically floating surfaces within a plasma acquire a negative charge due to the higher mobility of electrons as compared to positively charged ions.
This potential drop can result in wafer charging, leakage paths, and breakdown of dielectric layers (see FIG.
1
). This same problem occurs when employing ion beam techniques since such result in a positive charge on the wafer surface due to ion bombardment from the ion beam.
The problem due to the potential drop across the wafer is particularly pronounced when dealing with relatively thin dielectric layers such as about 40 to about 50 angstroms which are especially sensitive to being damaged. For instance, see Gabriel, “Measuring and Controlling Gate Oxide Damage from Plasma Processing”,
Semiconductor International
, July 1997, pp. 151-156. In fact, in view of the significance of this problem of gate oxide damage, in 1996 the American Vacuum Society, the IEEE/Electron Devices Society and the Japan Society of Applied Physics sponsored the first International Symposium on Plasma Process-Induced Damage.
It would therefore be desirable to provide a method to compensate for or eliminate this potential drop across the wafer or at least to minimize the possible detrimental effect attributed to this problem.
SUMMARY OF INVENTION
The object of the present invention is to at least minimize and if not, entirely eliminate, the potential drop across the semiconductor wafer and especially across a gate oxide during plasma and ion beam processing. Another object of the present invention is to minimize any harmful effects caused by potential drop across the wafer during processing.
The present invention provides a sacrificial structure and fabrication method which ensures that the potential drop across any gate oxide is at least reduced, if not entirely eliminated, during plasma and ion beam processing. The present invention provides a removable or sacrificial conductive strap or spacer, which provides a conductive path around insulating layer such as the gate oxide to thereby eliminate any damage to the insulating layer.
More particularly, the present invention is concerned with a semiconductor structure that comprises a semiconductor substrate; a conductor; and a first insulating layer separating the conductor and the substrate. A removable conductive strap is coupled to the conductor and the substrate in order to maintain a common voltage between the conductor and substrate during ion beam and/or plasma processing of the semiconductor structure. The removable conductive strap is electrically decouplable from between the conductor and the substrate upon completion of the ion beam and/or plasma processing. The present invention is also concerned with the semiconductor structure obtained upon electrically decoupling the conductive strap by thermal oxidation.
The present invention is also concerned with a process for fabricating a semiconductor structure which comprises providing a semiconductor substrate; providing a conductor on the substrate; and providing a first insulating layer separating the substrate and the conductor. A removable conductive strap is coupled to the conductor and substrate for maintaining a common voltage between the conductor and substrate during ion beam and/or plasma processing of the semiconductor structure. After fabricating, the conductive strap is decoupled from the conductor and substrate.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.


REFERENCES:
patent: 5292399 (1994-03-01), Lee et al.
patent: 5549784 (1996-08-01), Carmody et al.
patent: 5589002 (1996-12-01), Su
patent: 5594684 (1997-01-01), Hsue
patent: 5596207 (1997-01-01), Krishnan et al.
patent: 5599726 (1997-02-01), Pan
patent: 5600168 (1997-02-01), Lee
patent: 5618742 (1997-04-01), Shone et al.
patent: 5710438 (1998-01-01), Oda
patent: 5770506 (1998-06-01), Koh
patent: 5856698 (1999-01-01), Hu et al.
patent: 6107130 (2000-08-01), Fulford, Jr. et al.
patent: 6114734 (2000-09-01), Eklund
patent: 6146937 (2000-11-01), Hong
Gabriel, C.T., Measuring and Controlling Gate Oxide Damage from Plama Processing,Semiconductor International,Jul. 1997: 151-156.
Rossnagel, S.M., Glow Discharge Plasmas and Sources for Etching and Deposition,Thin Film Processes II,1991: 12-77.

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