Amplifiers – With semiconductor amplifying device – Including plural stages cascaded
Reexamination Certificate
2001-03-30
2002-04-02
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including plural stages cascaded
C330S253000, C333S217000
Reexamination Certificate
active
06366172
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor amplifier circuit and system including a cascode amplifier.
PRIOR ART
FIG. 3
illustrates an arrangement of a conventional semiconductor amplifier circuit
10
. The semiconductor amplifier circuit
10
amplifies an input signal V
IN
input to an input terminal IN and outputs the result to an output terminal OUT as an output signal V
OUT
.
The semiconductor amplifier circuit
10
includes a transistor
101
. The gate of the transistor
101
is connected to the input terminal IN. The source of the transistor
101
is grounded. The drain of the transistor
101
is connected to the output terminal OUT. The drain of the transistor
101
is supplied with a power supply voltage V
dd
via a load ZL.
FIG. 5
illustrates the results of a simulation of the operation of the semiconductor amplifier circuit
10
shown in FIG.
3
. Such a simulation is performed by using HSPICE, for example. The conditions for the simulation are as follows:
Transistor
101
: nMOS transistor
Frequency f of input signal V
IN
: 1 kHz
Load ZL: resistor of 1000&OHgr;
Output conductance gds of transistor
101
: 1 mS
Transconductance gm of transistor
101
: 24 mS
As shown in
FIG. 5
, through the semiconductor amplifier circuit
10
, an output signal V
OUT
is obtained by amplifying the input signal V
IN
by a factor of 12 (=ZL×gm/2).
However, in the structure of the semiconductor amplifier circuit
10
, the feedback capacitance C
gd
appears to be increased by a factor of about 12 as compared to effective capacitance due to a Miller effect. Thus, a larger current flows from the input terminal IN to the output terminal OUT as the frequency of the input signal V
IN
increases.
FIG. 4
illustrates the structure of a conventional semiconductor amplifier circuit
20
for reducing the Miller effect.
The semiconductor amplifier circuit
20
includes a cascode amplifier
500
. The cascode amplifier
500
includes the transistor
101
and a transistor
102
which are cascaded.
The gate of the transistor
101
is connected to an input terminal IN of the semiconductor amplifier circuit
20
. The source of the transistor
101
is grounded. The drain of the transistor
101
is connected to the source of the transistor
102
.
The gate of the transistor
102
is supplied with a fixed voltage V
b
. The fixed voltage V
b
is supplied from, for example, a DC power supply (not shown). A bypass capacitor C
1
is provided for removing an AC component of the voltage V
b
supplied from the DC power supply.
The source of the transistor
102
is connected to the drain of the transistor
101
. The drain of the transistor
102
is connected to an output terminal OUT of the semiconductor amplifier circuit
20
. The drain of the transistor
102
is supplied with the power supply voltage V
dd
via the load ZL.
FIG. 6
illustrates the results of a simulation of a drain voltage V
1
of the transistor
101
(i.e., a source voltage of the transistor
102
). Due to the cascode arrangement in which the transistor
101
and the transistor
102
are cascaded, the amplitude of the voltage V
1
is approximately equal to that of the input voltage V
IN
. Thus, there is no large current between the input terminal IN and the drain of the transistor
101
. As a result, the Miller effect is reduced.
The above-described cascode arrangement also enables one to obtain a large amount of electric power as the output of the transistor amplifier circuit
20
. This will be discussed below.
Generally, the maximum output power P
OUT
of an amplifier is expressed by (Expression 1):
P
OUT
~(
gm·V
IN
)
2
/G
OUT
(Expression 1)
where gm represents a transconductance of the amplifier, V
IN
represents a voltage of an input signal input to the amplifier, and G
OUT
represents an output conductance of the amplifier.
As will be appreciated from (Expression 1), P
OUT
is inversely proportional to G
OUT
.
As shown in
FIG. 3
, if the amplifier has a single transistor arrangement, G
OUT
=gds. Accordingly, by substituting G
OUT
=gds into (Expression 1), P
OUT
=(gm·V
IN
)
2
/ gds holds. On the other hand, if the amplifier (i.e., the cascode amplifier
500
) has a cascode arrangement as shown in
FIG. 4
, an approximation of G
OUT
=gds
2
/gm is possible in a band where the frequency of the input signal V
IN
is relatively low. Thus, by substituting G
OUT
=gds
2
/gm into (Expression 1), P
OUT
=(gm/V
IN
)
2
·gm/gds
2
holds in such a frequency band.
Thus, an amplifier having a cascode arrangement can obtain P
out
which is greater than that of an amplifier having a single transistor arrangement by a factor of gm/gds. For example, in the case where gm=10 mS and gds=1 mS, an amplifier having the cascode arrangement may obtain an amount of energy which is ten times greater than an amplifier having a single transistor arrangement.
As described above, an amplifier having a cascode arrangement has advantages of reducing the Miller effect and reducing output conductance. Due to these advantages, an amplifier having a cascode arrangement has been widely used.
However, in the case where the frequency of the input signal V
IN
is 100 MHz or more, there may be a frequency band wherein the output conductance of the semiconductor amplifier circuit
20
is negative. This is because there may be a frequency band wherein the output conductance G
OUT
of the cascode amplifier
500
is negative.
In the following description, the output conductance G
OUT
of an amplifier being negative (i.e., G
OUT
<0 holds) will be referred to as “the output conductance G
OUT
of an amplifier having a negative characteristic”.
FIG. 7
illustrates a structure of a small signal equivalent circuit of the cascode amplifier
500
. In the example shown in
FIG. 7
, the transistor
101
and the transistor
102
are assumed to be NMOS transistors of the same size. It is also assumed that the gate of the transistor
102
is grounded via the capacitor C
1
in order to reduce the Miller effect. The meanings of the symbols shown in
FIG. 7
are as follows.
C
gs1
: Gate-source capacitance of the transistor
101
C
gd1
: Gate-drain capacitance of the transistor
101
gm
1
: Transconductance of the transistor
101
gds
1
: Output conductance of the transistor
101
C
ds1
: Drain-source capacitance of the transistor
101
C
dsub1
: Drain-substrate capacitance of the transistor
101
R
sub1
: Substrate resistance from drain to ground of the transistor
101
C
gs2
: Gate-source capacitance of the transistor
102
C
gd2
: Gate-drain capacitance of the transistor
102
gm
2
: Transconductance of the transistor
102
gds
2
: Output conductance of the transistor
102
C
ds2
: Drain-source capacitance of the transistor
102
C
dsub2
: Drain-substrate capacitance of the transistor
102
R
sub2
: Substrate resistance from drain to ground of the transistor
102
Assuming that C
ds1
=C
ds2
=0, the output conductance G
OUT
of the cascode amplifier
500
is expressed by (Expression 2), in which Re(X) represents a real number portion of X:
G
OUT
=Re
(
Y
1
·Y
2
/(
Y
1
+Y
2
+gM
2
))+
Re
(
Y
3
) (Expression 2),
where Y
1
, Y
2
, and Y
3
are represented by (Expression 3), (Expression 4), and (Expression 5), respectively:
Y
1
=
Y
2
+
Y
3
=
gds
2
+
j
ω
C
ds2
+
j
ω
C
dsub2
/
(
1
+
j
ω
C
ds2
R
sub2
)
(
Expression
3
)
Y
2
=gds
2
+j&ohgr;C
ds2
(Expression 4)
Y
3
=j&ohgr;C
dsub2
/ (1
+j&ohgr;C
ds2
R
sub2
) (Expression 5)
where &ohgr;=2&pgr;f. Symbol f represents a frequency of the input siganl V
IN
. Symbol j represents an imaginary unit.
FIG. 9
illustrates the results of a simulation of the output conductance G
OUT
characteristic of the cascode amplifier
500
of the semiconductor amplifier circuit
20
. In
FIG. 9
, the horizontal axis represents the
Hayashi Joji
Kimura Hiroshi
Choe Henry
Matsushita Electric - Industrial Co., Ltd.
Pascal Robert
Snell & Wilmer L.L.P.
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