Telecommunications – Receiver or analog modulated signal frequency converter – Frequency modifying or conversion
Reexamination Certificate
1998-06-05
2001-04-17
Nguyen, Lee (Department: 2683)
Telecommunications
Receiver or analog modulated signal frequency converter
Frequency modifying or conversion
C455S323000, C455S326000, C327S113000, C327S119000, C327S359000
Reexamination Certificate
active
06219535
ABSTRACT:
BACKACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor circuit for performing amplification and frequency conversion of a high frequency signal in a mobile communication device, in particular, a cellular phone.
2. Description of the Related Art
Recently, as mobile communication devices such as cellular phones have become more prevalent, higher performance of the mobile communication devices, especially extended usage times have been demanded. As used herein, usage time is conversation time plus standby time. Since the recordable time is mainly determined by the power consumption of a semiconductor circuit for receiving high frequency signals (front end IC), the power consumption of the semiconductor circuit needs to be reduced.
A conventional semiconductor circuit for a cellular phone will be described with reference to FIG.
2
.
FIG. 2
is a block diagram of a semiconductor circuit
200
having three active elements. A low noise amplifier
1
and a local amplifier
2
, which are connected to each other in parallel, are connected to a mixer
3
in series. These three active elements
1
,
2
and
3
are each directly supplied with power by a constant voltage supply. The three active elements
1
,
2
and
3
each include a GaAs field effect transistor (hereinafter, referred to as an “FET”) in order to improve the high frequency characteristics.
The semiconductor circuit
200
operates in the following manner.
A high frequency signal having a frequency f
1
which is received by an antenna of a cellular phone is input to the low noise amplifier
1
through an input terminal
1
a
. The high frequency signal is amplified by the low noise amplifier
1
and then input to the mixer
3
. A constant frequency signal having a frequency f
2
which is generated by a local oscillator (not shown) is input to the local amplifier
2
through an input terminal
2
a
. The constant frequency signal is amplified by the local amplifier
2
and then input to the mixer
3
. A synthesis signal having an intermediate frequency f
1
-f
2
is output from an output terminal
3
a
of the mixer
3
.
The structure of the semiconductor circuit
200
shown in
FIG. 2
will be described in more detail with reference to FIG.
3
.
FIG. 3
is a circuit diagram illustrating a detailed configuration of the conventional semiconductor circuit
200
. The low noise amplifier
1
includes a FET
4
. The FET
4
is formed from GaAs. A gate electrode
4
g
of the FET
4
is grounded via a gate bias resistor
5
. A source electrode
4
s
of the FET
4
is grounded by a bypass capacitor
6
and a self-bias resistor
7
, which are connected to each other in parallel. The self-bias resistor
7
is provided in order to alleviate the instability in the amount of drain current which is caused by dispersion in the threshold voltage of the FET
4
.
The local amplifier
2
includes another FET
9
. A gate electrode
9
g
of the FET
9
is grounded via a gate bias resistor
10
. A source electrode
9
s
of the FET
9
is grounded via a bypass capacitor
11
and a self-bias resistor
12
, which are connected to each other in parallel.
The mixer
3
includes still another FET
14
. Gate electrodes
14
g
1
and
14
g
2
of the FET
14
are respectively grounded via gate bias resistors
15
and
16
. A source electrode
14
s
of the FET
14
is grounded via a bypass capacitor
17
and a self-bias resistor
18
, which are connected to each other in parallel.
A drain electrode
4
d
of the FET
4
is connected to the gate electrode
14
g
1
of the FET
14
via a coupling capacitor
8
, and a drain electrode
9
d
of the FET
9
is connected to the gate electrode
14
g
2
of the FET
14
via a coupling capacitor
13
.
The input terminals
1
a
and
2
a
and the output terminal
3
a
are respectively connected to the gate electrodes
4
g
and
9
g
and the drain electrode
14
d
.
As a power supply, a 3 V lithium battery
19
is used. The drain electrodes
4
d
,
9
d
and
14
d
are each supplied with a voltage of 3 V.
In accordance with a known method, the power consumption of the semiconductor circuit
200
is reduced by shortening the gate length of the FETs
4
,
9
and
14
to 0.6 &mgr;m and thus reducing the amount of the drain current.
FIG. 4
is a graph illustrating the relationship between the source-drain voltage (potential difference between the source electrode
4
s
and the drain electrode
4
d
) and the amount of the drain current of the FET
4
. As can be appreciated from
FIG. 4
, when the source-drain voltage is equal to or higher than the pinch-off voltage Vp, the amount of the drain current becomes constant. When the amount of the drain current is constant, the amplification ratio of the FET is constant. Accordingly, even when the source-drain voltage changes in the range of the pinch-off voltage Vp or higher, the amplification ratio of the FET is constant.
When the source-drain voltage increases, the power consumption of the FET increases. The power consumption is reduced without changing the amplification ratio of the FET, i.e., without changing the amount of the drain current by reducing the source-drain voltage in the range of no less than the pinch-off voltage Vp.
However, the conventional semiconductor circuit
200
of the cellular phone has a power supply including a 3 V lithium battery or three 1.2 V nickel hydrogen batteries connected in series to provide a voltage of 3.6 V in total. Therefore, the FET
4
operates at a voltage A in
FIG. 4
, which is significantly higher voltage than the pinch-off voltage Vp. Thus, the power supply used in the conventional semiconductor circuit
200
of the cellular phone provides a voltage which is excessively high for the FET included therein, and thus the power is wasted.
An FET having a gate length of less than 0.6 &mgr;m has a withstand voltage which is excessively low and sometimes causes abnormal operation when a voltage of 3 V is applied between the source and the drain.
SUMMARY OF THE INVENTION
A semiconductor circuit according to the present invention includes at least first and second field effect transistors. A source electrode of the first field effect transistor is connected to a drain electrode of the second field effect transistor via a first AC current blocking element and is also grounded via a bypass capacitor. A drain electrode of the first field effect transistor is connected to a power supply. A source-drain voltage of the first field effect transistor is equal to or higher than a pinch-off voltage of the first field effect transistor. A source-drain voltage of the second field effect transistor is equal to or higher than a pinch-off voltage of the second field effect transistor.
In one embodiment of the invention, the semiconductor circuit further includes at least one third field effect transistor and at least one second AC current blocking element. Each third field effect transistor is connected to one AC current blocking element. A drain electrode of the third field effect transistor is connected to the source electrode of the first field effect transistor via the first AC current blocking element. A source electrode of the third field effect transistor is connected to the drain electrode of the second field effect transistor via the second AC current blocking element. A source-drain voltage of the third field effect transistor is equal to or higher than a pinch-off voltage of the third field effect transistor.
In one embodiment of the invention, the semiconductor circuit further includes a gate voltage supply circuit. Gate electrodes of the first and third field effect transistors are connected to the gate voltage supply circuit. An end of the gate voltage supply circuit is connected to the power supply.
In one embodiment of the invention, the source electrode of the second field effect transistor is grounded via a resistor and a bypass capacitor which are connected to each other in parallel.
Thus, the invention described herein makes possible the advantage of providing a semiconductor circuit having
Ishida Hidetoshi
Ueda Daisuke
Matsushita Electronics Corporation
Nguyen Lee
Ratner & Prestia
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