Semi-smart DRAM controller IC to provide a pseudo-cache mode of

Details Semi-smart DRAM controller IC to provide a pseudo-cache mode of Semi-smart DRAM controller IC to provide a pseudo-cache mode of

1991-07-25

1992-10-27

Fleming, Michael R.

Static information storage and retrieval

Magnetic bubbles

Guide structure

3652385, 3642543, 364DIG1, 3649571, 364DIG2, G06F 1200

Patent

active

051596768

ABSTRACT:
A DRAM controller uses logic to selectively enable or disable a page mode of operation as a result of specific instructions from executing software, or upon some prediction of page mode efficiency based on past performance. An address multiplexer generates separate row and column addresses from the CPU address control lines, and to generate the necessary signals to control the timing of the RAS and CAS control signals that operate the DRAM. Page mode is automatically turned on or off based on a prediction of whether or not the next access will be at the same DRAM row address as the last one.

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