Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1999-08-14
2001-07-03
Everhart, Caridad (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S758000, C257S276000, C257S776000
Reexamination Certificate
active
06255712
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to high density integrated circuit (IC) devices. More particularly, this invention relates to very high density multilevel interconnect electronic structures, and processes of fabricating such structures, which are comprised of alternating via levels and wiring levels embedded in a gas dielectric medium, suitable for mounting on carriers such as multichip modules.
2. Background Art
The continuing drive toward reduction in dimensions and increase in the number and density of components within IC chips is inspired by increasingly more aggressive requirements of memory and logic. Smaller chip features provide higher bit density, lower operating voltages, lower energy consumption and faster device speed. Increased also are problems associated advanced IC miniaturization and the attendant closer proximity of circuit features to one another, including risk of shorting, crosstalk and capacitative coupling, among others. The highly dense integrated circuits of the future will require even narrower and longer conductor lines, tighter pitch via interconnects and lower dielectric constant values for the insulating medium, especially in the wiring levels. The lower the dielectric constant of the insulating medium, the faster the circuit speed.
As the design demands for the CMOS IC in particular become more aggressive, the need to reduce the dielectric constant of the insulating medium to a value closer to the ideal value of air, 1.0, becomes a necessity. Attempts have been described in the art to incorporate air into a solid dielectric matrix, as in the form of foam or microspheres. More recently, attention has turned to the possibility of employing air alone or some other gas as the dielectric medium in at least one level.
U.S. Pat. No. 5,789,559 issued Aug. 25, 1998 to Subhas Bothra and Liang Q. Qian describes the formation of air dielectric between metallization layers as a result of the removal of a temporary solid dielectric material by a liquid etchant, buffered hydrofluoric acid (BHF).
An article on pages 575-585 of the IBM Journal of Research and Development, Volume 42, No. Sep. 5, 1998, “Electrochemical processes for advanced package fabrication”, coauthored by S. Krongelb, J. A. Tornello and L. T. Romankiw includes a description of a multilevel interconnect IC in which polyimide functions as a temporary dielectric. The polyimide was removed by ashing in an oxygen-containing plasma. The IC chip also includes copper wiring, which was plated.
An article on pages 49-51 of the journal Electrochemical and Solid State Letters, published by the Electrochemical Society, Inc. 1(1), 1998, “Air Gaps for Electrical Interconnections”, coauthored by Paul L. Kohl, Qiang Zhao, Kaushal Patel, Douglas Schmidt, Sue Ann Bidstrup-Allen, Robert Shick and S. Jayaraman describes the removal of a sacrificial polymer by thermal decomposition within an encapsulated chip. The byproducts escape by diffusing through the encapsulant.
In the Technology News column on page 38 of the March 1999 edition of the journal Semiconductor International, Editor-in-Chief Peter Singer describes Toshiba's use of carbon dioxide gas dielectric in the wiring levels of an IC. The carbon dioxide is formed when the layer of carbon, which has been sputtered, is heated at 450 degrees C. in an oxygen atmosphere, resulting in the diffusion of oxygen to the carbon, where they combine to form CO2.
An article on pages 51, 52, 54, 57, and 58 of the February, 1999 issue of the journal Solid State Technology, “Air gaps lower k of interconnect dielectric”, coauthors Ben Shieh, Krishna Saraswat, Mike Deal and Jim McVittio describe results of their modelling of air dielectric in structures having a variety of aluminum conductor line dimensions. Their simulation predicts a 40%-50% reduction in capacitance due to the air dielectric.
In the present invention, wet processing can be limited to photolithographic processes, such as resist removal, which are conventionally used successfully and without contaminating the IC structure. Rather than using aggressive solvents to remove a temporary, sacrificial dielectric material, an isotropic oxygen etch is used to remove the sacrificial dielectric material cleanly. Where a electroplating can be used to deposit such metals as copper and gold for wiring and interconnect vias in the present invention, dry deposition is preferred because extra steps such as those involved in establishing a barrier to electromigration of the metal into silicon are not required and because some useful metals and alloys are not amenable to plating. A wide variety of dielectric gasses can be protectively incorporated into the IC chip of the present invention. High temperature decomposition techniques play no role, nor is it necessary to fabricate passivation layers, such as on the substrate level. The present invention uniquely uses diamond-like carbon or diamond, preferably deposited by CVD, rather than, for example, a polymer or a silicon oxide as the temporary, sacrificial dielectric layer material. Since CVD diamond is a stronger material than polyimide or other dielectric polymer, use of the CVD diamond in the present invention will facilitate planarization by chemical-mechanical polishing (CMP). CVD diamond has the further advantage superior ability to conduct heat away from the IC chip which it encloses, in particular when a limited amount of CVD diamond is permitted to remain within the fabricated structure.
The present invention includes the removal of sacrificial CVD diamond in a gas etchant, leaving gas-filled gaps to function as the permanent dielectric medium in, for example, a CMOS IC, a procedure not described in the art. The process of the present invention avoids any attack on or contamination of the elements of the IC structure and obviates any need to protect the gate level substrate by passivation, allowing the gate level the benefit of the low dielectric gas medium and avoiding passivation steps. Furthermore the present invention describes a means of encapsulating the gas dielectric and an encapsulated CMOS IC not found in the art. The encapsulant eliminates diffusion of moisture or impurities into the encapsulated structure and confines the gas within. Several different gases can be used as alternative permanent dielectric media. These and other advantages and distinctions will be more fully evident infra.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a multilevel interconnect CMOS IC chip having a gas insulating medium whose dielectric constant approaches or equals the ideal value of air.
It is a further object of the invention to employ a CVD diamond sacrificial dielectric in conjunction with removal of the sacrificial dielectric by an isotropic oxygen etch to produce a very low-k IC chip.
It is a further object of the invention to provide an encapsulated multilevel interconnect CMOS IC chip having a gas insulating medium which is protected from exchange of material with the external ambient and away from which heat is readily conducted.
It is a further object in an alternative mode of the invention to permit CVD diamond to remain in selected areas of the chip in order to provide additional structural support and thermal conductivity.
It is a further object in an alternate mode of the invention to provide strategically located support structure in the form of pillars or studs in the process of forming an encapsulated structure.
These and other objects are achieved according to the present invention in which, except for standard photolithographic steps, dry processing steps produce a high density CMOS IC which includes a gaseous dielectric medium interlevel and intralevel. The fabrication of the IC involves first including diamond-like carbon (DLC), diamond or preferably CVD diamond as a sacrificial dielectric material. Upon completion of the chip, prior to the deposition of final encapsulant, the sacrificial dielectric is removed harmlessly and selectively through openings in a hard mask top
Clevenger Lawrence A
Hsu Louis L.
Anya Igwe U.
Everhart Caridad
International Business Machines - Corporation
Olsen Judith D.
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