Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Having only two terminals and no control electrode – e.g.,...
Reexamination Certificate
2002-06-06
2004-10-05
Vo, Tuyet T. (Department: 2821)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Having only two terminals and no control electrode , e.g.,...
C257S114000, C257S684000, C250S338400, C250S336200, C359S199200
Reexamination Certificate
active
06800877
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the interconnection of semiconductor devices, and more particularly to the use of free space electrons to couple semi-conductor and microprocessing devices.
BACKGROUND OF THE INVENTION
It has been a desire for a long time and continues to be such in the computer arts to produce a computing machine which can process large amounts of data in minimum time. Typically, instructions and data are forced to flow serially through a single, and hence central, processing unit (CPU). The bit width of the processor's address/data bus (i.e., 8, 16 or 32 bits wide) and the rate at which the processor (CPU) executes instructions (often measured in millions of instructions per second, “MIPS”) tend to act as critical bottlenecks which restrict the flow rate of data and instructions. CPU execution speed and bus width must be continuously pushed to higher levels if processing time is to be reduced.
Attention is being directed to a different type of computing architecture where problems are solved not serially but rather by way of the simultaneous processing of parallel-wise available data using multiple processing units. These machines are often referred to as parallel processing arrays. The advantage of parallel processing is simple. Even though each processing unit may have a finite, and therefore speed-limiting, processor bandwidth, an array having a number of such processors will have a total computation bandwidth of a number of times the processor bandwidth.
The benefits derived from increasing the size of a parallel array are countered by a limitation in the speed at which messages can be transmitted to and through the parallel array, i.e., from one processor to another or between one processor and an external(input/output) device. Inter-processor messaging is needed so that intermediate results produced by one processing unit can be passed on to another processing unit within the array. Messaging between the array's parallel memory structure and external I/O devices such as high speed disks and graphics systems is needed so that problem data can be quickly loaded into the array and solutions can be quickly retrieved. The array's messaging bandwidth at the local level, which is the maximum rate in terms of bits per second that one randomly located processor unit can send a message to any other randomly located processor unit.
Hopefully, messaging should take place in parallel so that a multiple number, of processors are simultaneously communicating at one time thereby giving the array a parallel messaging bandwidth of multiple times the serial bandwidth. Ideally, the simultaneous communication should be equal to the number of processors in the array so the processors are simultaneously able to communicate with each other. Unfortunately, there are practical considerations which place limits on the speed and number of processors which can communicate with each other. Among these considerations are the maximum number of transistors and/or wires which can be defined on a practically-sized integrated circuit chip, the maximum number of integrated circuit's and/or wires which can be placed on a practically-sized printed circuit board and the maximum number of printed circuit boards which can be enclosed within a practically-sized card cage. Wire density is typically limited to a finite, maximum number of wires per square inch and this tends to limit the speed of processor communications in practically-sized systems.
If the ultimate goal of parallel processing is to be realized (unlimited expansion of array size with concomitant improvement in solution speed and price/performance ratio), ways must be found to maximize the parallel messaging bandwidth so that the latter factors do not become new bottlenecking limitations on the speed at which parallel machines can input problem data, exchange intermediate results within the array, and output a solution after processing is complete.
SUMMARY OF THE INVENTION
In accordance with the teachings of the present invention, an apparatus and method for electrically connecting semi-conductor devices in parallel which overcome the deficiencies of the prior art is disclosed. The apparatus and method employs a vacuum chamber and first and second semi-conductor components. In this regard, the first and second semi-conductor components are coupled to the vacuum chamber. The first semi-conductor component is connected to a first free space electron transmitter and a first free space electron receiver, while the second semi-conductor component is connected to a second free space electron transmitter and a second free space electron receiver. The free space electron transmitters and a free space electron receivers are disposed within the vacuum chamber. The first transmitter is configured to transmit a signal from the first semi-conductor component to the second free space electron receiver while the second transmitter is configured to transmit a signal from the second semi-conductor component to the first free space electron receiver.
In one embodiment, an electronic component has first and second substrates. A first member is disposed between the first and a second substrates, which defines a vacuum chamber. First and second semi-conductor components are coupled to the substrates. The first and second semi-conductor components are further connected with free space electron transmitters and free space electronic receivers which are disposed with the vacuum chamber. The semi-conductors are configured to transmit signals to each other through the free space electron receivers and transmitters.
In another embodiment, an electronic component having first and second substrates is disclosed. A first member is disposed between the first and a second substrates, that defines a vacuum chamber. First and second semi-conductor components are coupled to the substrates. The first and second semi-conductor components are further connected with free space electron transmitters and free space electronic receivers, which are disposed with the vacuum chamber. The semi-conductors are configured to transmit signals to each other through the free space electron receivers and transmitters. The free space electron transmitters have a cathode array, which includes a plurality of cathodes, each of the cathodes operable to emit electrons. Additionally the free space electron transmitter includes an anode or focusing grid. The anode grid includes a plurality of aiming anodes, each of the aiming anodes are operable to aim an electron beam formed from the electrons emitted from one of the cathodes. Additionally the free space electron transmitter has a focusing grid and an accelerating grid disposed between the cathode array and the free space electron receiver. The focusing grid and accelerating grid are operable to control the flow of electrons from each of the cathodes to the receiver.
In yet another embodiment, a parallel processing computer is disclosed. The parallel processing computer has first and second substrates, and a vacuum chamber disposed between the first and a second substrates. A first microprocessor is coupled to the first substrate, and is coupled to a first free space electronic transmitter. The first free space electron transmitter is disposed within the vacuum chamber. A second semi-conductor component is coupled to the second substrate, and is coupled to a second free space electron transmitter and a second free space electron receiver. The second free space electron transmitter and a second free space electron receiver are disposed within the vacuum chamber. The first free space electron transmitter is configured to transmit a signal from the first microprocessor component to the second free space electron receiver.
Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for p
Silzars Aris
Victor Michel N.
Exaconnect Corp.
Harness & Dickey & Pierce P.L.C.
Vo Tuyet T.
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