Semi-conductor circuit arrangement

Details Semi-conductor circuit arrangement Semi-conductor circuit arrangement

2006-01-24

2006-01-24

Nguyen, John B (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S144000, C341S154000

Reexamination Certificate

active

06989778

ABSTRACT:
A semi-conductor circuit arrangement for a continuous time sigma delta modulator for adding analog input signals to a digital fed back signal and for quantizing the totalled signal comprises a voltage to current conversion circuit (10), an adding circuit (20) with a resistor ladder, a quantizing circuit (40) with comparator elements (45) and a digital to analog conversion circuit (30). For each comparator element (45) its respective input signal is formed by a voltage which is released between a tap in front of a corresponding tapping resistor (22) in a first string of the resistor ladder and a tap in front of a corresponding tapping resistor (22) in a second string of the resistor ladder.

REFERENCES:
patent: 4316178 (1982-02-01), Shibayama et al.
patent: 5070332 (1991-12-01), Kaller et al.
patent: 6882294 (2005-04-01), Linder et al.
Moyal et al., “A 700/900mW/Channel CMOS Dual Analog Front-End IC for VDSL with Integrated 11.5/14.5dBm Line Drivers”, 2003 IEEE Solid-State Circuits Conference, Digest of Technical Papers, Feb. 12, 2003, (10 pages).
Dörrer et al., “A 10-Bit, 4mW Continuous-Time Sigma-Delta ADC for UMTS in a 0.12 μm CMOS Process”, Proceedings of the 2003 Symposium on Circuits and Systems, ISCAS, May 2003, pp. I-1057 to I-1060 (4 pages).

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