Semi-conductor chip packaging method and semi-conductor chip hav

Details Semi-conductor chip packaging method and semi-conductor chip hav Semi-conductor chip packaging method and semi-conductor chip hav

1993-04-26

1994-11-22

Thomas, Tom

Fishing, trapping, and vermin destroying

437211, 437215, 437217, 437220, H01L 2160

Patent

active

053669320

ABSTRACT:
A semiconductor chip having a cellular topography and a method of packaging a cellular semiconductor chip includes plural interdigitated metal gate runners that overlie and contact selected gate electrodes on the chip surface, each of the gate runners having an integral widened area to enable a package-carried gate electrode contact foil to be bonded thereto. The gate runner widened areas are relatively small and have little impact on chip active area. The plural gate runners have portions that underlie a package-carried power electrode contact foil and that are separated therefrom by a nonbondable, insulating layer. The gate runners may be deposited on the chip in the same step and from the same material as the power electrode. The portion of the power electrode on the chip surface that underlies the package-carried gate electrode contact foil is separated therefrom and available for use as active area of the chip. Package lid-to-chip alignment tolerances may be relaxed as they are not dictated by alignment of the lid-carried gate contact foil with the gate electrode on the chip.

REFERENCES:
patent: 4824804 (1989-04-01), Cheng
patent: 5084404 (1992-01-01), Sharpe-Geisler
patent: 5135890 (1992-08-01), Temple et al.
patent: 5139972 (1992-08-01), Neugebauer et al.
patent: 5192716 (1993-03-01), Jacobs
patent: 5248901 (1993-09-01), Temple
patent: 5258647 (1993-11-01), Wojnarowski et al.

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