Semaphore register including ownership bits

Details Semaphore register including ownership bits Semaphore register including ownership bits

1980-09-15

1983-04-19

Ruggiero, Joseph F.

Boots, shoes, and leggings

G06F 1516

Patent

active

043807984

ABSTRACT:
A semaphore register for use in a peripheral controller includes a semaphore bit which when not set indicates the availability of a shared resource, an internal ownership bit which when set indicates ownership of the resource by a peripheral controller and an external ownership bit which when set indicates ownership of the resource by a host processor. If the semaphore is clear, upon receipt of a read signal from the peripheral controller, the semaphore bit and the internal ownership bit are set. Upon receipt of a read signal from the host processor, the semaphore bit and the external ownership bit are set. Arbitration logic includes means responsive to simultaneous reads by the host processor and the peripheral controller for indicating to the host processor that the resource is unavailable thus giving priority to the peripheral controller. The semaphore bit may be reset by write signals from either the peripheral controller or the host processor.

REFERENCES:
patent: 3919692 (1975-11-01), Kronies et al.
patent: 4096572 (1978-06-01), Namimoto
patent: 4115851 (1978-09-01), Nagano et al.
patent: 4124304 (1980-07-01), Shimizu et al.
patent: 4145739 (1979-03-01), Dunning et al.
patent: 4214305 (1980-07-01), Tokita et al.
Duke, K. A. and Messina, B. V., Multiprocessing Storage Conflict Resolution Technique, IBM Technical Disclosure Bulletin, vol. 15, No. 10, Mar. 1973, pp. 3232-3233.

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