Semaphore memory to reduce common bus contention to global memor

Details Semaphore memory to reduce common bus contention to global memor Semaphore memory to reduce common bus contention to global memor

1988-06-17

1991-09-17

Anderson, Lawrence E.

Boots, shoes, and leggings

364229, 3642281, 3642468, G06F 1516, G06F 1316

Patent

active

050500724

ABSTRACT:
The invention greatly reduces common bus contention by allowing the semaphore test bit and set operations to be performed on each CPU's local bus. The semaphore lock bits are stored locally in high speed SRAM on each CPU, and coherency of the lock bits is maintained through a bus monitoring logic circuit on each CPU. A CPU wishing to take possession of a semaphore performs a local read of its semaphore memory, and spins locally until the lock bit is reset at which time it performs a local write to set the bit. When the semaphore lock bit is written, it will be updated locally, and at the same time the write operation will be sent out over the common bus. The bus monitoring logic on every other CPU will recognize the write operation and simultaneously update the corresponding lock bit in each local semaphore memory. This ability to read spin locally relieves the common bus from the great amount of traffic that occurs in typical systems that maintain the semaphore lock bits in common global memory.

REFERENCES:
patent: 4412285 (1983-10-01), Neches
patent: 4570217 (1986-02-01), Allen et al.
patent: 4574350 (1986-03-01), Starr
patent: 4975833 (1990-12-01), Jinzaki

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