1991-12-13
1993-11-09
Fleming, Michael R.
395325, 395425, 395200, G06F 1516
Patent
active
052611060
ABSTRACT:
The present invention provides a test and set bypass mechanism which allows access to a semaphore while eliminating memory bandwidth degradation due to the traditional "spin-locking" problem. Generally, a storage and comparison structure in a processor, such as a content addressable memory (CAM), is used to store the address of the semaphore whenever it is requested. Thus, the process/processor, or other processors in a multiprocessor system, then need only check to see if the semaphore address is present in its respective storage and comparison structure. Consequently, there is no need to make multiple memory transactions for failed access of the semaphore, and hence, effective memory bandwidth is increased.
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Lau Te-Li
Lentz Derek J.
Fleming Michael R.
Hafiz Tariq R.
S-MOS Systems, Inc.
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