Self verifying logic system

Details Self verifying logic system Self verifying logic system

1981-10-29

1984-09-11

Malzahn, David H.

Excavating

324 73PC, G06F 1122

Patent

active

044714840

ABSTRACT:
The invention provides internal self testing within an integrated circuit chip at all points along the logic chain. Internal stimulus generators and supervisory control circuits for the generators formed integrally within a VLSI chip are utilized together with integrally formed multiple fault detectors to provide self testing of the logic chain, mechanical interconnection failures, and power and clock pulse checking. The invention is utilizable in conjunction with either single or duplicate logic, which latter may be either duplicate complementary logic or duplicate functional logic. The multiple fault detectors provide a multiplicity of error signals which are multiplexed within the chip to produce encoded output error signals each of which designates the fault which has been detected within the chip. The invention eliminates the need for sophisticated ancillary test systems for diagnostic and go
o-go or confidence testing for hardware at the chip, board and system level. In a system these encoded error signals may be routed to error handling logic which receives encoded error signals from a large number of places, such as a group of chips or circuit cards, and by correlating the information contained in the encoded error signals is able to identify the source of the error as a particular VLSI chip, the interconnections between VLSI chips, a particular circuit card, a power supply line to a circuit card or a group of such cards, or other faults.

REFERENCES:
patent: 3815025 (1974-06-01), Jordan
patent: 3873818 (1975-03-01), Barnard
patent: 4001818 (1977-01-01), Radichel et al.
patent: 4066882 (1978-01-01), Esposito
patent: 4139818 (1979-02-01), Schneider
patent: 4180772 (1979-12-01), Buelow et al.
patent: 4205301 (1980-05-01), Hisazawa

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