Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control
Patent
1996-11-22
1999-08-03
Mis, David
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular error voltage control
331 1A, 331 2, 331 14, 331 10, 331 16, 331 25, 331 18, 331 49, 327157, H03L 708, H03L 7099, H03L 710, H03L 718
Patent
active
059330589
ABSTRACT:
A self-tuning clock recovery phase-locked loop (PLL) includes a programmable divide-by-M, a phase-frequency detector, a programmable voltage-controlled oscillator (VCO), a programmable divide-by-N, and a PLL tuning circuit, which in normal mode operation, perform as a conventional PLL. When the frequency of an input clock signal to the PLL changes by more than a threshold value, however, the PLL tuning circuit causes the PLL to be retuned for the new frequency by adjusting offset and gain parameters in the PLL such that the input voltage to the VCO is mid-way in its input voltage range when the output clock frequency of the PLL is approximately equal to the input clock frequency multiplied by a closed loop gain of the PLL, so that the VCO is operating in a linear region having wide dynamic frequency range.
REFERENCES:
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"Digital Audio Interface," International Satandard CEI/IEC 958, Premiere Edition, First Edition, 1989-03, pp. 5-49.
"Digital Audio Interface," International Standard CEI/IEC 958, Amendment 1, 1993-02, pp. 3-35.
Brochure entitled: "Six-Channel Dolby Digital Surround Processor (ZR38500)," Zoran Corporation, pp. 1-36 (Feb. 1996).
Feldman Neil David
Hadas Tzach
Pinto Victor
Zandman Yaakov Arie
Mis David
Zoran Corporation
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