Self-timing method for adjustment of a sampling phase in an...

Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data

Reexamination Certificate

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C375S354000, C375S359000, C375S360000, C375S362000, C327S141000, C327S160000, C327S163000

Reexamination Certificate

active

08068572

ABSTRACT:
This invention discloses a self-timing method for phase adjustment. An analog signal is digitized at a first and second phase with respect to the symbols comprised in an analog signal in order to obtain first and second quantized samples. Then a first counter out of a first plurality of counters is increased if said first quantized sample has a first digital value to which said first counter is associated. Moreover a second counter out of a second plurality of counters is increased if a second quantized sample has a second digital value to which the second counter is associated. Finally the sampling phase is adjusted based on the values of the counters of the first and second plurality of counters. Moreover a digitizing, self-timing circuit is disclosed.

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