Self-timing four-phase clock generator

Details Self-timing four-phase clock generator Self-timing four-phase clock generator

1994-11-16

1996-11-26

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Phase shift by less than period of input

327295, 327400, 331 57, H03K 304, H03K 513

Patent

active

055789544

ABSTRACT:
A four phase clock generator, which can be employed to operate a charge pump, is configured using coupling elements that ensure that the four phases are non-overlapping. Each of the circuits used to generate one of the four phases of the clock signal consists of a logic block, a buffer block whose delay can be controlled, and a cascade of inverters for amplifying the signal produced by the circuit. The buffer block acts both to invert the signal produced by the logic block, and to delay the signal output by the logic block by an amount which can be varied based on control signals which mirror a current source. The amount of signal delay produced by the buffer is used to adjust the relative timing of the rising and falling edges of each of the four phases of the clock signal (and hence the frequency of the signal) in response to the demand placed upon a charge pump which is driven by the clock signal generator. Two of the clock signal phase circuits have delay elements that have substantial delays that can be used to alter the clock frequency, where the delays can be varied in response to the control signal. The delay introduced by the logic block can also be controlled by the control signal. This provides a clock whose frequency is proportional to the control signal.

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Kuriyama, et al, "A 5V-Only 0.6 .mu.m Flash EEPROM With Row Decoder Scheme in Triple-Well Structure," 1992 IEEE International Solid-State Circuits Conference, pp. 152-153.

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