Self-timing control circuit

Details Self-timing control circuit Self-timing control circuit

1999-06-04

2001-05-29

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

Reexamination Certificate

active

06239635

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a self-timing control circuit for generating a control clock synchronized in a prescribed phase relationship to a master clock; and to a self-timing control circuit with a simple circuit structure which can lock on in a short time and which can carry out highly precise timing control for a high speed clock.
2. Description of the Related Art
Synchronous DRAM is one of the latest high speed memory devices. Such a high speed device is supplied command signals, address signals, data signals, and the like in synchronized with a clock by a controller; outputs a data signal in synchronized with the clock. As noted above, high speed operations are realized through the use of the clock as a strobe signal.
In such a device, an external clock is input once into the device and a control signal, being a strobe signal, is generated; in such a case, the phase of the control signal becomes unmatched with the supplied clock due to the delay characteristics of the internal circuitry. For this reason, a self-timing control circuit, to generate a control clock, synchronized in a prescribed phase relationship to a master clock, is established within the device.
Conventional self-timing control circuits utilize a delay locked loop circuitry (DLL circuitsry below) for generating a control clock delayed by one or more cycles of the supplied clock.
FIG. 1
shows the DLL circuitry constituting a conventional self-timing control circuit. In
FIG. 1
, the external clock signal CLK is supplied by means of an input buffer
1
to a variable delay circuit
2
and a variable delay circuit
4
, and is supplied as a first input for a phase comparison circuit
7
at the same time. A delay clock signal d-i-clk is generated from the clock signal c-clk, which is input to the variable delay circuit
4
, passes through a dummy data output buffer
5
and a dummy input buffer
6
. This delay clock signal d-i-clk is supplied as a second input to the phase comparison circuit
7
. The phase comparison circuit
7
compares the phases of the two input signals c-clk and d-i-clk and outputs the results of the comparison to the delay control circuit
8
. The delay control circuit
8
controls the amount of the delay of the variable delay circuit
2
and variable delay circuit
4
according to the phase comparison results. The amount of the delay, controlled by the delay control circuit
8
, is applied to the clock signal c-clk input to the variable delay circuit
2
, the clock signal c-clk is supplied to the data output buffer
3
as a control clock n
0
. The data output buffer
3
is synchronized with the control clock signal n
0
supplied thereto, takes up data DATA, and outputs this data externally as the data output data Dout.
Moreover, the dummy data output buffer
5
is unnecessary when the control clock n
0
is used as a strobe signal for the input buffer.
Such DLL circuits are noted in detail in Japanese Patent Application No. 8-339988 (Dec. 19, 1996 application, Japanese Patent Laid-open Publication No. 10-112182, laid open Apr. 28, 1998), for which the present applicants have already applied.
In the aforementioned DLL circuits, however, the variable delay circuits
2
,
4
comprise a plurality of serially connected unit delay circuits. Consequently, highly precise control of the timing of the control clock generated requires that the amount of the delay of the unit delay circuits be small and the number of those circuits be large. As a result, the variable delay circuits become large in scale and occupy increased area on the chip, whereby the variable delay circuits become an obstacle to higher integration of integrated circuit devices.
Furthermore, highly precise timing control is necessary in order to have operating speeds in excess of 100 MHz, for example. Even with large scale variable delay circuits, the device cannot handle timing control with finer precision than the amount of delay of the unit delay circuits, as long as digitally control the timing wherein the amount of delay of the unit delay circuits is a variable unit.
Also, a problem is that locking on requires a long period of time when power is turned on or when the device is returning from a powered down state, because the conventional DLL circuits are reset once and then perform a feedback operation for phase matching.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a self-timing control circuit which can control the timing of the control clock with high precision and with small scale circuitry.
It is another object of the present invention to provide a self-timing control circuit including analog control of the timing of the control clock.
It is another object of the present invention to provide a self-timing control circuit which can enter a locked on state within a short period of time from reset.
A self-timing control circuit relating to the present invention comprises a clock cycle counting circuit for counting ocillation pulses during a period corresponding to a cycle of the master clock and generating a clock cycle count value. The count value for a period corresponding to the cycle of the master clock is calculated with this clock cycle counting circuit. The self-timing control circuit further comprises a control clock generating portion for generating the control clock, as timed by synchronizing with the master clock, starting a count of the oscillation pulses, and counting up to the clock cycle count value. As a result, the control clock generated is delayed from the master clock by the time taken to count to the measured count value. The timing of the control clock is delayed from the master clock by one cycle or an integer multiple thereof.
With this constitution, the period from reset to lock on can be shortened because the delay time of the control clock generating portion is set to a period corresponding to a cycle of the supplied master clock.
A self-timing control circuit relating to another invention further comprises a delay time adjusting circuit, for synchronizing with the master clock, starting a count of oscillation pulses, and generating an oscillator control signal, according to the adjusting count value at the end of a period corresponding to a cycle of the master clock. The frequency of the aforementioned pulses is controlled so that the adjusting count value matches the aforementioned clock cycle count value, according to the oscillator control signal.
Consequently, it is not necessary to establish a large scale variable delay circuit and a delay control circuit corresponding thereto, as the prior art. Also, because fine adjustment of the oscillator frequency is comparatively easy, the range of timing adjustment can be narrowed, making possible highly precise timing control.
Furthermore, in another invention, the frequency of the oscillation clock can be controlled to a high or low frequency, depending on whether the clock cycle count value is high or low. As a result, control clocks corresponding to the frequencies of a wide range of master clocks can be generated without an increase in the number of counters installed. Therefore, different types of oscillators for generating the oscillation clock are installed and those oscillators are switched among depending on the size of the clock cycle count value. Another possibility is to switch operations within the oscillator.
In order to achieve the aforementioned objects, the present invention is a self-timing control circuit for generating a control clock, synchronized in a prescribed phase relationship to a master clock, comprising:
a clock cycle counting circuit for counting oscillation pulses for a period corresponding to a cycle of the master clock and generating a clock cycle count value; and
a control clock generating portion for starting a count of the oscillation pulses in synchronized with the master clock, and generating the control clock at a timing when counting up to the clock cycle count value.
With such a constitution, the period corresponding to

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