Self-timing circuit

Details Self-timing circuit Self-timing circuit

1986-12-19

1988-06-14

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307481, 307451, 307452, 307269, H03K 1900, H03K 19096

Patent

active

047514078

ABSTRACT:
A timing circuit is disclosed for use with an external circuit that provides a precharge/evaluation complete signal indicative of precharge completion and evaluation completion. The timing circuit is responsive to a clock signal and the precharge/evaluation complete signal provided by the external circuit, and includes a clock enabling circuit responsive to the clock signal and the precharge/evaluation complete signal for providing a clock enable signal having first and second states respectively indicative of (a) a predetermined condition wherein evaluation has been completed and the clock signal is at a predetermined level, and (b) precharge completion. A level shifting circuit is responsive to the clock signal and the clock enable signal and provides a phase control signal to the pseudo CMOS circuit, where such phase control signal defines (a) a precharge phase in response to said clock enable signal indicating the predetermined condition and the clock signal providing a predetermined transition, and (b) an evaluation phase in response to the precharge/evaluation complete signal indicating completion of precharging. A latching circuit is responsive to the clock enable signal and the clock signal for selectively latching the phase control signal in its respective phases.

REFERENCES:
patent: 4040015 (1977-08-01), Fukuda
patent: 4569032 (1986-02-01), Lee
patent: 4570083 (1986-02-01), Nakaizumi
patent: 4617480 (1986-10-01), Au
"Receiver for Clocked or Pseudo-Clocked Cascode Voltage Switch Logic", IBM Technical Disclosure Bulletin, by Miersch et al., vol. 27, No. 10B, Mar. 1985.

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