Communications: electrical – Digital comparator systems
Reexamination Certificate
2002-05-08
2003-11-11
Wambach, Margaret R. (Department: 2816)
Communications: electrical
Digital comparator systems
Reexamination Certificate
active
06646544
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to an address compare circuit to test the equivalence of two addresses each made up of the same number of bits. Furthermore, the speed at which this compare is performed is of the highest priority.
Trademarks: IBM is a registered trademark of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.
BACKGROUND
In computer design, it is common to compare two addresses in order to determine the validity of a preceding or subsequent operation. For example, the address (of a portion of data needed to execute an instruction) is compared to an address stored in a directory register to determine if a local Cache SRAM is holding a copy of the data.
In general, there are two primary ways to implement the compare logic:
1. Bit-by-bit compare, then “AND” each Bit-by-bit compare together: Before a compare operation begins, the output of the compare circuit indicates a mismatch or “MISS” state. Once the operation begins, the two addresses are compared “bit by bit”. Next, each bit compare is “ANDed” together forming a “AND” tree usually taking 2 or more stages. If the address is the same, the compare circuit indicates a match (or “HIT”). Otherwise an inactive state or “MISS” is indicated by the compare circuit.
2. Bit-by-bit miscompare, then “OR” each Bit-by-bit miscompare together: Before a compare operation begins, the output of the compare circuit indicates a match or “HIT” state. Once the operation begins, the two addresses are compared “bit by bit”. Next, each bit miscompare is “ORed” together forming a “OR” tree usually taking 2 or more stages. If the address is the same, the compare circuit output will maintain the a match (or “HIT”). Otherwise an MISS” is indicated by the compare circuit.
The disadvantage of first method is the “AND” logic uses series transistors which tend to be slow to operate. Although, this method can use traditional static CMOS logic gates which are relatively easy to implement, the speed disadvantage is hard to over come.
The disadvantage of the second method is the compare circuit indicates a “HIT” prior to the actual compare operation. For, example, if downstream logic is dynamic in nature, dynamic logic may not tolerate a HIT at its inputs during its pre-charge. This overlap of signals or “collision” can cause false HIT related operations to occur. Nevertheless, the “OR” logic is preferred, since it uses parallel transistors and tend to operate quickly.
To take advantage of the second method's speed while avoiding the collision problems, a HIT evaluation clock (HIT clock) is introduced. The HIT clock is used to trigger the last stage of the “OR” tree. As a result, the compare circuit output will start in the MISS state and will only switch to the HIT state when both addresses match and the HIT clock is active. However, the timing of the HIT clock is not easily accomplished.
Generally, in there patented art, U.S. Pat. No. 6,353,558, it is noted that specifically describes a method for reading and writing a memory array during the same clock cycle with the same decoded address. The present invention, which is concerned mainly with the self timed nature of a high-speed compare function differs and the “to compare” function is not addressed in this art, and furthermore, the preferred embodiment provides new self timed features which allow for higher speed operation.
Another patent, specifically U.S. Pat. No. 6,055,611, generally relates to the enabling of memory cells and more particularly relates to effectively replacing defective portion of memory array with despair portion, again does not address the preferred embodiment featues, no how the self timed compare function is achieved, nor how the self timed features allows for higher speed operation. This is also true of U.S. Pat. No. 5,765,194 which generally relates to a compare circuit and to timing between an address “MISS” and with a “forced” MISS.
SUMMARY OF THE INVENTION
The preferred embodiment of the invention provides an improvement in an address compare circuits and provides a compare circuit that can reliably self-timed off of the input data insuring proper compare timing with respect to the arrival of the two addresses being compared. This circuit provides a way to generate a very accurate internal HIT evaluation clock; therefore, the compare circuit reduces the extra setup time needed to guarantee all address data bits are valid. Furthermore, the HIT evaluation clock can be delayed to increase the arrival times of input data, resulting in a greater operating window.
Also, the improved address compare circuit of the preferred embodiment allows for large “OR” structures which reduce circuit stages resulting in faster overall circuit performance. Furthermore, when the number of bits being compared is increased, the overall delay increase is marginal due to the “OR” structures.
The present invention primarily uses dynamic input data ( i.e. the inputs “return-to-zero” at the end of each cycle); however, if the inputs originate as “static” inputs to the compare circuit, then these static inputs are first preconditioned at the input receiver (i.e. a input repowering circuit), so when they arrive at the compare circuitry, they now have the necessary characteristic of a “return-to-zero” at the end of each cycle.
This preferred embodiment lends itself to very large compare compare operations (60 inputs and grater) with only marginal delay increase when the number of bits being compared is increased. There is use of dynamic input data, ( i.e. “return-to-zero” at the end of each cycle); however, if the inputs originate as “static” inputs to the Compare circuit, then these static inputs are first preconditioned at the input receiver (i.e. re-buffering circuit), so when they arrive at the Compare circuit, they now have the necessary characteristic of a “return-to-zero” at the end of each cycle. The self-timed hit evaluation clock, which is generated by the rising edges of the input data, triggers an evaluation of the compare circuit. This evaluation clock circuit is designed is such a way so that it tracks the compare circuit delay even when simulation models have wide tolerance's. This is accomplished by mimicking the actual compare circuit with similar transistor topologies.
REFERENCES:
patent: 5765194 (1998-06-01), McBride
patent: 6054918 (2000-04-01), Holst
patent: 6055611 (2000-04-01), Wright et al.
patent: 6353558 (2002-03-01), Lattimore et al.
Augspurger Lynn L.
Wambach Margaret R.
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