Self-timed latch circuit for high-speed very large scale integra

Details Self-timed latch circuit for high-speed very large scale integra Self-timed latch circuit for high-speed very large scale integra

1998-12-22

2000-12-19

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327208, H03K 3356, H03K 3037

Patent

active

061631930

ABSTRACT:
A self-timed latch circuit according to the present invention includes a first inverter for inverting a set signal, a second inverter for inverting a reset signal, a first main driver driven by an output signal from the second inverter and the set signal, a second main driver driven by an output signal from the first inverter and the reset signal and a static latch cross-coupled with first and second output terminals of the first and second main drivers. The self-timed latch circuit according to the present invention reduces the power consumption and increases the operation speed of the circuit by removing a back-to-back connection and a serial connection of transistors applied to the conventional art. Further, since the static latch consists of cross-coupled inverters, the self-timed latch circuit according to the present invention prevents signal fighting during the logic transition of output signals and also reduces a leakage current generated during the operation of the circuit.

REFERENCES:
patent: 5124568 (1992-06-01), Chen et al.
patent: 5760634 (1998-06-01), Fu
David Renshaw et al., "Race-Free Clocking of CMOS Pipelines Using a Single Global Clock;" IEEE Journal of Solid-State Circuits, vol. 25, No. 3, Jun. 1990, pp. 766-769.
Morteza Afchahi et al., "A Unified Single-Phase Clocking Scheme for VLSI Systems;" IEEE Journal of Solid-State Circuits, vol. 25, No. 1, Feb. 1990, pp. 225-233.

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