Self-timed interface for a network of computer processors interc

Details Self-timed interface for a network of computer processors interc Self-timed interface for a network of computer processors interc

1996-06-24

1997-12-02

Shah, Alpesh M.

Boots, shoes, and leggings

3952002, 364229, 3642382, 36424294, 364DIG1, G06F 1300

Patent

active

056946120

ABSTRACT:
A massively parallel system has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. Digital data is transmitted at high speeds via the parallel bus to provide a scalable communications network for parallel processing systems while eliminating precise bus length and system clock rates as a critical or limiting factor.

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