Pulse or digital communications – Synchronizers – Network synchronizing more than two stations
Patent
1995-05-26
1996-10-22
Tse, Young T.
Pulse or digital communications
Synchronizers
Network synchronizing more than two stations
375371, 371 1, 327163, H04B 110
Patent
active
055685269
ABSTRACT:
A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.
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patent: 5313501 (1994-05-01), Thacker
Jacobs, G M, "A Fully Asychronous Digital Signal Processor Using Self-timing Circuits," IEEE Journal of Solid-State Circuits, vol. 25 No. 6 Dec. 1990 pp. 1526-1531.
Capowski Robert S.
Casper Daniel F.
Ferraiolo Frank D.
Jordan Richard C.
Laviola William C.
Augspurger Lynn L.
International Business Machines - Corporation
Marhoefer Laurence J.
Tse Young T.
Webster Bryan E.
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