Self timed interface

Details Self timed interface Self timed interface

1994-06-17

1998-11-03

Chin, Stephen

Pulse or digital communications

Synchronizers

Network synchronizing more than two stations

375371, 371 1, 327163, H04L 700

Patent

active

058320474

ABSTRACT:
A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.

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Jacobs, B.M., "A Fully Asynchronous Digital Signal Processor Using Self-Timing Circuits," IEEE Journal of Solid-State Circuits, vol. 25 No. 6: Dec. 1990 pp. 1526-1531.

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