Self-timed interconnect speed-up circuit

Details Self-timed interconnect speed-up circuit Self-timed interconnect speed-up circuit

1993-10-22

1995-10-03

Hudspeth, David R.

Induced nuclear reactions: processes, systems, and elements

Testing, sensing, measuring, or detecting a fission reactor...

Vessel monitoring or inspection

326 86, H03K 1704

Patent

active

054555213

ABSTRACT:
A circuit style, which may be employed in fast, area-efficient, flexible programmable interconnect architectures, or in logic circuits, is disclosed. In one embodiment, a plurality of internally delayed logic circuits, each having a single network node, is connected to the intermediate nodes of a programmable interconnect architecture. Each speed-up circuit monitors the logic level on the network node. When a circuit detects a substantial change in logic level, it temporarily enforces that change by connecting its network node to either the high or the low logic level. Thus, on each node, a low-impedance enhancement of the signal driving the node temporarily appears. This causes the potential on neighboring nodes, connected through conducting programmable switches, to change towards the new level, and their speed-up circuits in turn temporarily enforce the new level. Thus, a forced high-to-low or low-to-high level change on a node quickly propagates to its connected nodes.

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Ogura, T., et al., "A 20-kbit Associate Memory LSI for Artificial Intelligence Machines", IEEE Journal of Solid State Circuits, V. 24, No. 4, Aug. 4, 1989, p. 1018.

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