Self-timed differential comparator

Communications: electrical – Digital comparator systems

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G06F 702

Patent

active

060549181

ABSTRACT:
A multiple-bit comparator achieves a fast operating speed and accurate operation through the connection of multiple individual-bit comparison devices to a first line and the connection of a timing device to a second line. The first line and the second line are differentially sensed to generate a signal designating whether all bits match or not. In some embodiments, the replica timing device is timed using a timing signal replicating the application of data to the individual-bit comparison devices and generates a signal on the second line that is delayed in comparison to the multiple-bit comparison signal on the first line by reduced sizing of the timing device in comparison to the individual-bit comparison devices. In some embodiments, a differential comparator includes a sense amplifier that is self-timed rather than utilizing a strobe signal to supply timing. In some embodiments, the sense amplifier includes a cross-coupled device that sources current between differential sides of the sense amplifier. A typical cross-coupled device supports a bias current, consuming power when the circuit is inactive. However, the present sense amplifier includes a precharge switch that stops current drain in the sense amplifier when the amplifier is inactive.

REFERENCES:
patent: 4843339 (1989-06-01), Burt et al.
patent: 5391938 (1995-02-01), Hatsuda
patent: 5471188 (1995-11-01), Chappell et al.

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