Self-timed clocked analog to digital converter

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

Reexamination Certificate

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Details

C363S020000, C363S129000, C323S222000, C365S193000

Reexamination Certificate

active

07834793

ABSTRACT:
An SAR analog-to-digital converter performs bit decisions in each of a plurality of clock cycles. A sense circuit monitors signals input to a latch within a comparator of the ADC and, when the signals are sufficient to establish a bit decision, the sense circuit terminates a currently active clock cycle causes a bit decision to occur in advance of a normal expiration of the clock cycle. If the signals are insufficient to establish a bit decision prior to a default expiration time of the clock cycle, the clock cycle concludes at the default expiration time.

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patent: 2008/0100490 (2008-05-01), Chatal et al.
patent: 2009/0102780 (2009-04-01), Brown
patent: 2009/0273739 (2009-11-01), Brown
Shuo-Wei Michael Chen and Robert W. Brodersen, “A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13- m CMOS”, IEEE Journal of Solid-State Circuits, vol. 41, No. 12, Dec. 2006, pp. 2669-2680.
Brian P. Ginsburg and Anantha P. Chandrakasan, “Dual Time-Interleaved Successive Approximation Register ADCs for an Ultra-Wideband Receiver”, IEEE Journal of Solid-State Circuits, vol. 42, No. 2, Feb. 2007, pp. 247-257.
Naveen Verma and Anantha Chandrakasan, “An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes”, IEEE Journal of Solid-State Circuits, vol. 42, No. 6, Jun. 2007, pp. 1196-1205.
International Search Report dated Jun. 7, 2010, in counterpart international application No. PCT/US2009/065697.

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