Self-timed address decoder for register file and compare...

Details Self-timed address decoder for register file and compare... Self-timed address decoder for register file and compare...

2000-02-08

2001-07-31

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S233100, C365S194000

Reexamination Certificate

active

06269045

ABSTRACT:

TECHNICAL FIELD
The present invention relates in general to data processing systems, and in particular, to an address decoder.
BACKGROUND INFORMATION
To achieve high speed operation of a register file, fast read and write address decodes are essential. Register file decodes are usually done by pre-decoding the addressing lines by ANDing two or more addresses together, then distributing these ANDed lines to the wordline drivers where final decode is done by ANDing again. When the decoded signals are stable, a clock signal then enables the wordline drivers allowing the one wordline driver with the proper decode to activate a DECOUT line to the storage cells of the register file which then either reads or writes the data in the storage cell. Since the speed of the register file is rated in terms of the arrival of the address to the data coming out, the faster the address can be decoded, the faster the register file. The arrival of the addresses are measured relative to a clock signal, which tells the register file that the addresses are now valid and the register file access can now proceed.
FIG. 9
illustrates typical circuitry for implementing address decoders for accessing such register files. The address signals are received by AND circuits
900
for decoding.
FIG. 10
illustrates further detail of each AND circuit
900
. A clock generator
1001
must distribute clock signals CLK
1
and CLK
2
throughout the circuit
900
, accounting for skew and process variations across the circuit. The first clock signal CLK
1
activates the decoding of address signals A
1
, A
2
, and A
3
by clocked AND circuits
1002
to produce the {overscore (select)} signal, which is then received by decode driver circuit
1003
along with another one of the address signals A
0
. Decode driver
1003
is activated by the second clock signal CLK
2
to produce output DECOUT. In circuit
900
, it must be guaranteed that clock signal CLK
1
rises and there is sufficient time for all {overscore (select)} signals to be resolved before the rising of the second clock signal CLK
2
. Then each of circuits
900
must guarantee that signal CLK
2
falls before signal CLK
1
falls.
FIGS. 11 and 12
illustrate specific circuit implementations of circuits
1002
and
1003
, respectively, using dynamic circuit architecture.
What is needed in the art is an address decoder that does not have the problems associated with the prior art address decoder illustrated in
FIGS. 9-12
through its implementation of two separate clock signals.
SUMMARY OF THE INVENTION
The present invention addresses the foregoing needs by providing an address decoder that evaluates a portion of the incoming address signals, insures that this evaluation stabilizes, and then drives the evaluation as an output. This is accomplished using one clock signal, instead of the two used within the prior art. To insure that the evaluated signal stabilizes, the portion of the circuit that drives the output is activated by a delayed clock signal produced by delaying the original clock signal.
In another embodiment of the present invention, substantially the same circuitry can be utilized within a self-timed address decoder where the clock signal is replaced by a reset signal.
In yet another embodiment, a multi-port CAM can benefit from the increase in speed afforded by the circuit techniques of the present invention.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.


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