Self-timed activation logic for memory

Details Self-timed activation logic for memory Self-timed activation logic for memory

2003-04-25

2004-08-31

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Powering

Conservation of power

C365S194000, C365S233100

Reexamination Certificate

active

06785184

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to the field of memory. Particularly, the invention relates to clock timing for accessing memory locations.
BACKGROUND OF THE INVENTION
Memory integrated circuit devices are well known. Memory cells can be read only (ROM), randomly accessible (RAM), static (SRAM), semi-static, dynamic (DRAM), programmable (PROM, EPROM, EEPROM), volatile, non-volatile (NVRAM) or of another memory type. The technology of transistor circuits used to form the memory cells can be varied as well. Exemplary types of technologies used include NMOS, PMOS, CMOS, bipolar, bi-CMOS or another circuit or technology type.
Typically, the memory cells are arranged in an array or matrix of memory cells and are accessed using column and row address decoders. The row address decoder typically generates a signal on a word line to select a desired row of memory cells. The column decoder then selects desired bit lines for certain memory cells in the row. Depending upon whether a write or read operation is desired, data is written into the selected memory cells or read out of the selected memory cells respectively. In either case, parasitic capacitance on the bit lines requires that charges be removed or stored thereon.
Memory is oftentimes used to store data or operands upon which operations are performed over and over to obtain results. Access to a memory that stores the data or operands is very frequent, particularly in digital signal processing applications where the data may be digital data samples representing the communication over a communications channel. Because operands are frequently used, there are frequent accesses to the memory that stores them. A high rate of access into a memory tends to consume larger amounts of power than a memory than is infrequently accessed. This is due in part to the more frequent charging and discharging of charges stored on parasitic capacitances in the memory. The equation for computing power dissipated by a capacitor is
P
=
1
2
⁢
CV
2
⁢
F
.
It is desirable to lower power consumption over that of the prior art.


REFERENCES:
patent: 6618313 (2003-09-01), Nguyen et al.

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