Self-testing method for irregular CMOS switching structures with

Details Self-testing method for irregular CMOS switching structures with Self-testing method for irregular CMOS switching structures with

1995-08-16

1996-09-10

Karlsen, Ernest F.

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

371 225, G01R 3126

Patent

active

055549411

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

The present invention relates to a self-testing method and apparatus for irregular CMOS switching structures.


BACKGROUND INFORMATION

A known self-testing method (Koenemann, B.; Mucha, J.; Zwiehoff, G.; Built-In Logic Block Observation Techniques; IEEE Int'l Test Conference, 1979) uses linear feedback shift registers to produce real-time test stimuli and to compress the test responses. In this case, the data flow is observed at internal test points of complex digital circuits. Since the reaction of the circuit to the test stimuli is detected only at the primary outputs of the circuit in this method, bridge faults cannot reliably be identified, specific stuck-at faults can be identified only with difficulty and redundant stuck-at faults cannot be identified at all. In other known self-testing methods (Chang, T.; Wang, C.; Hsu, J.; Two Schemes for Detecting CMOS Analog Faults; IEEE Journal of Solid-State Circuits, Vol. 27, No. 2, Feb. 1992; or Favalli M. et al.; Novel Design for Testability Schemes for CMOS IC's; IEEE Journal of Solid-State Circuits, Vol. 25, No. 5, Oct. 1990), built-in current sensors are used for sensing the static current consumption (Iddq monitoring).


SUMMARY OF THE INVENTION

The present invention provides a method which comprises a combination of self-testing with linear feedback shift registers and the self-testing principle of sensing the static current consumption in conjunction with partitioning the circuit to be tested (combinational logic). Different test modes can be implemented depending on the circuitry (of PH1-PH3). A distinction must be made first of all between a "logic test" and an "Iddq test" (sensing the static current consumption). In the logic test, the reaction of the circuit to the test stimuli of the input register is observed at the primary outputs of the circuit (output register). This test is executed in real time and permits the identification of stuck-at, stuck-open and delay faults and also, in some instances, of bridge faults.
In the Iddq test, the reaction of the circuit is observed by the partial current sensors. In this case, short-circuit faults (stuck-at faults and bridge faults) can be reliably identified up to a maximum magnitude R.sub.smax, provided that they have been stimulated. Since the observation is carried out by the current sensor in the Iddq test, the fault only has to be stimulated (controllability). As a result of the omission of the observability problem which occurs in the logic test, this leads to an increased fault discovery rate for each test vector or to a reduction in the total number of test vectors required.
Furthermore, the following advantages emerge from using the current sensor: of the defects in CMOS circuits, latter result in logic faults, for example gate oxide shorts, and hence increased reliability of the circuit,
Consequently, the combination of the two test principles, the "logic test" and the "Iddq test," exhibits the advantage of high detectability of parametric faults (delay faults, high-resistance bridge faults) and functional faults (stuck-at, stuck-open and low-resistance bridge faults). This advantage can be favorably implemented with an additional hardware expense of about 25%. In this case, there is a resulting trade-off between the additional hardware expense, the resistance R.sub.smax of the identifiable short-circuit fault and the test speed for the current sensor.
In an extended refinement of the present invention, in comparison with the known methods and apparatus, precharging of a local node (N1) and evaluation by means of a NOR gate effect for the current sensor an increase in the test speed in conjunction with low circuit complexity. The observed high-resistance nodes (VVDD and N1) are local nodes which can be designed to be short, with the result that interference immunity of the testing method is thereby ensured. The evaluation by the global NOR gate is carried out ratiometrically for these reasons (by means of TPX).


BRIEF DESCRIPTION OF THE DRAWINGS

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REFERENCES:
patent: 5097206 (1992-03-01), Perner
patent: 5294883 (1994-03-01), Akiki et al.
patent: 5392293 (1995-02-01), Hsue
patent: 5459737 (1995-10-01), Andrews
patent: 5483170 (1996-01-01), Beasley et al.

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