Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2001-11-01
2004-04-20
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S058000, C324S763010, C324S765010
Reexamination Certificate
active
06725171
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and system for full parametric testing of the drive and receive capability of bi-directional driver/receiver-stages, and in particular of bi-directional input/output-stages of a semiconductor chip.
BACKGROUND OF THE INVENTION
The testing of semiconductor chips in general is a very complex task because test devices must be fine enough in order to be coupled to the enormous number of chip signal input/output pins which are available to test the chip with a given test scheme.
Current and next generation semiconductor product chips have an increasingly large number of signal I/O stages to achieve the performance and complexity requirements imposed by the specific technical progress intended with each new generation. This trend, in conjunction with the required high quality of the products, results in the need for very costly test equipment to reach all of the signal input/output stages at the tester in order to have the stages tested adequately.
‘Adequate testing’ means to enable for full parametric testing of the physical drive/receive capabilities of the driver/receiver system of an I/O stage. It should be noted that this is far more than the self-test facilities being implemented on-chip in prior art, as for example disclosed in U.S. Pat. No. 5,541,935, or in an exemplary I/O stage as depicted in
FIG. 1
, which will be discussed later below.
The ‘drive capability test’ basically means to give an answer to the question if a driver device has the physical (i.e. electrical) properties required for driving a desired voltage level reflecting one of the three states, i.e. low, high and high-impedance state, abbreviated herein as HZ-state, from the driver stage input to its output. In particular, testing the parametric specifications of a driver device consists of testing the resistance of the transistor device in pass mode, as well as in lock mode.
The receive capability of the receiver stage is essentially determined by whether the receive hysteresis has specified threshold levels LPUL (Least Positive Up Level for ‘0’) and MPDL (Most Positive Down Level for ‘1’) which can be realized during normal operation of the stage. If the respective latch stores a ‘1’ and the value shall be overwritten to ‘0’, a voltage level must be applied at its input which is smaller than the MPDL because of the hysteresis problem being present in this situation. On the other hand, if the latch stores a ‘0’ which shall be overwritten to ‘1’, an input voltage is required which is at least greater than LPUL. Thus, ‘full parametric testing’ means to qualify a respective driver/receiver stage to determine if (and to quantify, in particular, how good) the drive and receive processes can be achieved with an I/O stage.
The above mentioned test equipment required for full parametric testing is large and expensive. In particular, the coupling between test apparatus and chip is difficult because of the enormous number of I/O stages to be tested. Nearly each new chip generation requires a new expensive test apparatus in particular to test the quality of the I/O stages.
In order to simplify the full parametric chip testing a method was introduced, the so-called “reduced pin test method”. The basic idea used in this prior art approach is to couple an intermediate, connective device having a reduced number of pins between the test apparatus and the chip to be tested. The testing scheme was then a ‘structurized scheme’, i.e. a scheme in which a selectively chosen subset of chip signal I/Os connected to a low pin count test apparatus and a specific set of test patterns, applied only to this test I/O interface was decided to be sufficient to test the respective chip and in particular by having the unconnected signal I/Os testing themselves by receiving their own driven value.
A prior art I/O stage is illustrated below with reference to FIG.
1
.
FIG. 1
shows a simplified scheme of a prior art bi-directional signal I/O stage
10
having a built-in ‘digital’ self-test feature by which minimum qualitative properties of driver
18
receiver
24
system can be tested by driving both values ‘0’ and ‘1’ to node
14
(generally a connective pad denoted as PAD in the figures), and by receiving it correspondingly in receiver
24
and signal line
26
RDATA.
This kind of self-test, however, is of limited coverage as mentioned above with reference to U.S. Pat. No. 5,541,935, because it does not tell anything about the ‘analog’, i.e. the electrical properties of the I/O stage (the driver and receiver capabilities, DC-Ohm or AC-impedance, and hysteris behavior) as it will be described later below. Thus, applying this kind of built-in self-test, the driver as well as the receiver part can not be fully tested against the parametric specifications of the I/O stage like drive capability and/or receiver threshold levels.
I/O stage
10
further consists of signal line
12
DDATA as a signal input representing the logical data value (‘0’ or ‘1’) which has to be driven out by driver logic
18
to node
14
denoted as PAD as the off-chip connection thereof. Signal line
16
carries a signal denoted as ACT which is the signal input used for ACTivating and turning off the driver when signal I/O stage
10
has to be in receive mode. P-type
20
and N-type
22
output stage field effect transistors, referred to herein and denoted in the drawing as P and N (FETs) are connected to node
14
PAD.
The P and N transistor devices depicted in
FIG. 1
are illustrated in a simplified manner in order to improve clarity. In reality, each device
20
and
22
consists of a number of single transistors of the I/O stage, which is in turn often called an ‘I/O book’.
Receiver device
24
denoted as ‘rec’ converts the voltage levels applied at node
14
PAD to logical ‘0’ and ‘1’ values at signal line
26
denoted as RDATA which is usually stored into a latch for further test evaluation but could also be carried out in a different way to the test apparatus. For simplification of the following disclosure it will be assumed that rec
24
already contains a latch function to store the test result.
Having implemented the limited self-test capability mentioned above, signal I/O stage
10
receives its own driven output signal. In this situation the off-chip connection PAD has no loading applied so that driver logic
18
may achieve the receiver threshold levels LPUL (Least Positive Up Level for ‘0’) and MPDL (Most Positive Down Level for ‘1’) too easily, which may result in undertesting. Further, a defect mis-aligning the detection levels of receiving stage
24
can rarely be found in the receiver area which may result in undertesting, as well.
As can be appreciated now by a person skilled in the art, due to the problems mentioned above there is a need to have all signal I/O stages connected to the above mentioned external test system in order to enable the testing for the full parametric specifications of drive and receive capability.
As mentioned in the prior art, the parametric drive capability test can be tested only with the external load connected to PAD in
FIG. 1
provided by expensive external test circuitry. Without such external test circuitry, however, no test of the parametric specifications of the driver/receiver system can be performed, neither for chips constructed compatible to reduced pin technology nor for chips being incompatible with it.
BRIEF SUMMARY OF THE INVENTION
It is thus an object of the present invention to improve the testing of driver and that of receiver stages, and in particular that of combined stages, and in particular that of semiconductor chip I/O stages.
Although the present invention has a very broad scope implied by its inherent technical abstractness, it will be discussed in here primarily with reference to bi-directional chip input/output (I/O) stages, since this is the most obvious technical area to apply the present invention and to draw significant technical and economical advantages immediately from it.
According to its broadest aspect, the present inventi
Baur Ulrich
Eckelman Joseph
Hui David TinSun
Torreiter Otto Andreas
Barbee Manuel L
Canale Anthony J.
Hoff Marc S.
International Business Machines - Corporation
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