Self test semiconductor memory with error correction capability

Details Self test semiconductor memory with error correction capability Self test semiconductor memory with error correction capability

1985-09-03

1987-08-25

Smith, Jerry

Excavating

G06F 1110

Patent

active

046897925

ABSTRACT:
A self testing ROM includes an information array (10) for storing data therein and a parity array (12) for storing associated parity information for each of the data words. The data is accessed and multiplexed for input to a block code error detect circuit (30) for detecting the error and outputting an error syndrome on a bus (32). The error syndrome is input to an error correct circuit (34) for correction of the accessed data during a first pass through the error detect circuit (30). This corrected data is then input to latches (39) and (41). The latched data is then input back to the block code error detect circuit (30) during a second pass to determine if the data was corrected. If not, this indicates that there were too many errors to be corrected by the error detection algorithm. This is detected with a system error detect circuit (43) during the second pass through the block code error detect circuit (30). Each of the addresses in the arrays (10) and (12) are stepped through and processed through the block code error detect circuit (30) twice.

REFERENCES:
patent: 4175692 (1979-11-01), Watanabe
patent: 4319356 (1982-03-01), Kocol
patent: 4335459 (1982-06-01), Miller
patent: 4336611 (1982-06-01), Bernhardt
patent: 4523314 (1985-06-01), Burns
Conzala, et al., "Error Correction Without Speed Degradation", IBM TDB, vol. 10, No. 8, 1/1968, pp. 1275-1276.

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