Self-test for leakage current of driver/receiver stages

Details Self-test for leakage current of driver/receiver stages Self-test for leakage current of driver/receiver stages

2001-11-01

2004-08-10

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

06774656

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method and system for providing a test for leakage current for driver/receiver stages, and in particular for bi-directional input/output stages of a semiconductor chip.
BACKGROUND OF THE INVENTION
The testing of semiconductor chips in general is a very complex task because test devices must be fine enough in order to be coupled to the enormous number of chip signal input/output pins which are available to test the chip with a given test scheme.
Current and next generation semiconductor product chips have an increasingly large number of signal I/O stages to achieve the performance and complexity requirements imposed by the specific technical progress intended with each new generation. This trend, in conjunction with the required high quality of the products, results in the need for very costly test equipment to reach all of the signal input/output stages at the tester in order to have the stages tested adequately.
Adequate testing includes testing for input/output leakage current of driver/receiver stages of an I/O stage.
The above mentioned test equipment required for the adequate testing is large and expensive. In particular, the coupling between test apparatus and chip is difficult because of the enormous number of I/O stages to be tested. Nearly each new chip generation requires a new expensive test apparatus in particular to test the quality of the I/O stages.
In order to simplify chip testing in general, and in particular the testing of the driver and receiver capability, a method was introduced, the so-called “reduced pin test method”. The basic idea used in this prior art approach is to couple an intermediate, connective device having a reduced number of pins between the test apparatus and the chip to be tested. The testing scheme was then a ‘structurized scheme’, i.e., a scheme in which a selectively chosen subset of chip signal I/Os connected to the low pin count test apparatus and a specific set of test patterns, applied only to this test I/O interface was decided to be sufficient to test the respective chip and in particular by having the unconnected signal I/Os testing themselves by receiving their own driven value.
A prior art I/O stage is described below with reference to
FIG. 1
in order to show the prior art situation and the problems associated with it.
FIG. 1
shows a simplified scheme of a prior art bi-directional signal I/O stage
10
having a built-in ‘digital’ self-test feature by which minimum qualitative properties of driver
18
/receiver
24
system can be tested by driving both values ‘0’ and ‘1’ to node
14
(generally a connective pad denoted as PAD in the figures) and by receiving it correspondingly in receiver
24
and signal line
26
RDATA.
This kind of self-test, however, is of limited coverage only because it does not tell anything about the ‘analog’, i.e., the electrical properties of the I/O stage and, in particular, nothing about the leakage current between off-chip connective node
14
and supply voltage VDD, or ground, or any other relevant voltage potential.
I/O stage
10
further consists of signal line
12
DDATA as a signal input representing the logical data value (‘0’ or ‘1’) which has to be driven out by driver logic
18
to node
14
denoted as PAD as the off-chip connection thereof. Signal line
16
carries a signal denoted as ACT which is the signal input used for ACTivating and turning off the driver when signal I/O stage
10
has to be in receive mode. P-type
20
and N-type
22
output stage field effect transistors, referred to herein and denoted in the drawing as P and N (FETs) are connected to node
14
PAD.
The P and N transistor devices depicted in
FIG. 1
are illustrated in a simplified way only, in order to improve clarity. In reality, each device
20
and
22
consists of a number of single transistors, which is in turn often called a ‘signal driver’.
Receiver device
24
denoted as ‘rec’ converts the voltage levels applied at node
14
PAD to logical ‘0’ and ‘1’ values at signal line
26
denoted as RDATA often further connected to a Master/Slave latch. Having implemented the limited self-test capability, signal I/O stage
10
receives its own driven output signal. In this situation where the signal I/O stage receives its own driven output signal by having the driver in low impedance mode, a potential defect causing leakage paths or erroneous driver high impedance, i.e. OFF state, behavior may not be detected explicitly.
In particular, the off-chip connection PAD is not fully tested for leakage paths to VDD, GND or any other potential, nor can a defect, causing a low impedance at the P or N device, be detected when it should be in high-impedance mode, abbreviated herein as HZ-mode. Whenever the signal I/O stage is in HZ-mode, the resulting voltage level at PAD is unpredictable, i.e. floating, so that no valid logical expect value at signal evaluation line
26
RDATA can be defined to be tested for.
BRIEF SUMMARY OF THE INVENTION
It is thus an object of the present invention to improve the testing of driver and that of receiver stages, and in particular that of combined stages, and in particular that of chip I/O stages.
According to its broadest aspect, the present invention provides a method for qualifying a leakage current to be tolerable or not, the leakage current being present in a test area of a hardware circuit, and in particular of a driver/receiver stage, or input/output stage, respectively, which consists of the test area between a first tap node, and a second node being able to be forced to a voltage potential of a value, ie. ground, or supply voltage level Vdd, or any other predetermined voltage level. The method consists of the steps of: a) shutting off any operational current inflow into the test area, b) generating an evaluable voltage difference between the first tap node and the second node, the voltage difference being characteristic for the leakage current, c) qualifying the leakage current as tolerable in dependence of the resulting voltage at the first tap node. The characteristic voltage difference can be a voltage drop in a test path consisting of a specifically added switching element acting as an Ohm-resistor such as a transistor switched in pass mode having a predetermined operational resistivity and the test area connected in series to the resistor.
A key idea of the present invention is thus to provide an on-chip self-test feature, which provides valid voltage levels at the off-chip connection node PAD for a good device, which are convertible by the receiver to predictable logic states at the evaluation line RDATA. In the case of a current leakage or a HZ fail, the voltage level at PAD will not meet this requirement and will lead to a mismatch of the logical value expected at the signal line RDATA.
Advantageously, this can be done as follows. Two dedicated support transistor devices are added into the prior art switching scheme together with a simple control logic for selectively controlling the two transistors according to a predetermined test scheme to be performed autonomously on the chip without any test device external to the chip being required. The test input is fed via input lines into the control logic and the test result can be read from a result signal line.
The first of the two support devices is denoted as ‘support device Up’ and abbreviated as SDU, whereas the second support device is denoted as ‘support device down’, further abbreviated as SDD. Both devices are transistors of small size, the resistivity parametrics of which are defined as a function of the maximum allowed leakage current, further referred to as ‘Ileak’ (max) and as a function of the predetermined ‘receiver rec’ voltage levels, further referred to herein as MPDL (Most Positive Down Level) and ‘LPUL’ (Least Positive Up Level) including a respective predetermined guardband thus yielding the V PAD voltages VL=MPDL−guardband and VH=LPUL+guardband.
In the case of an intolerable leakage current on a path

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