Self-test for charge redistribution analog-to-digital converter

Details Self-test for charge redistribution analog-to-digital converter Self-test for charge redistribution analog-to-digital converter

1998-08-28

2001-07-31

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S144000

Reexamination Certificate

active

06268813

ABSTRACT:

The present invention relates generally to analog-to-digital converters (ADCs) and, in particular, to apparatus and methods providing self-testing for successive approximation ADCs of the charge redistribution, weighted capacitor array type.
BACKGROUND OF THE INVENTION
A successive approximation ADC produces an n-bit digital output by comparing a sampled and held analog input signal with the output of an internal digital-to-analog converter (DAC), using a successive approximation logic and registers controlled in such a way that the DAC output value converges towards the held input value. This is typically accomplished by splitting the voltage range in half in consecutive clock cycles to determine where the input signal lies. Thus, an eight-bit successive approximation ADC, for example, converges to a final result by taking eight consecutive “guesses,” or successive approximations. An example of such ADC is described in U.S. Pat. No. 4,679,028, incorporated herein by reference.
One approach to successive approximation ADCs is the charge redistribution, weighted capacitor array ADC, an example of which is described in James L. McCreary and Paul R. Gray, “All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques,”
IEEE Journal of Solid State Circuits
, Vol. SC-10, No. 6, December 1975, at pages 371-379 and U.S. Pat. No. 4,399,426, both incorporated herein by reference. In this approach, a plurality of capacitors are used as the precision elements of a charge redistribution array and given binary weighted values. The capacitors are charged by the analog input signal, then sequentially switched for successive comparisons of the stored input signal with corresponding successive divisions (halvings) of an applied reference signal. The sequence of comparator outputs from the comparison steps provides the sequence of digital output bits, most to least significant bit, of the digital word representation of the analog input.
FIG. 1
shows a charge redistribution analog-to-digital converter (ADC)
10
in accordance with the prior art. ADC
10
has a capacitor array
12
interconnected via conductor
14
to a comparator
16
. The output
18
of comparator
16
is connected to control, sequence and storage circuit
20
which produces the digital data bits output on DATA OUT lines
22
a
through
22
e
. Circuit
20
is comprised of successive approximation logic circuits which activate, control and sequence switches (such as MOS transistor switches) via conductors
24
a
through
24
n
to capacitor array
12
.
As shown in
FIG. 2
, capacitor array
12
is comprised of a plurality of capacitors
26
-
36
, connected in parallel. Capacitors
26
-
34
are binary weighted so that capacitor
26
corresponding to the most significant bit (MSB) has the largest value (
16
C), capacitor
28
corresponding to the next bit has a value (
8
C) which is one-half the value of capacitor
26
, capacitor
30
corresponding to the next bit has a value (
4
C) which is one-half the value of capacitor
28
, capacitor
32
corresponding to the next bit has a value (
2
C) which is one-half the value of capacitor
30
, and capacitor
34
which corresponds to the least significant bit (LSB) has a value (C) which is one-half the value of capacitor
32
. There is one additional capacitor
36
having the same value (C) as the value of the least significant bit capacitor
34
.
Capacitors
26
-
36
have their top plates commonly connected to line
42
to one input (the non-inverted input) of voltage comparator
16
and to a switch S
1
which, when connected to point A, is open and, when connected to point B, is closed to connect the top plates to ground. The bottom plates of capacitors
26
-
36
are connected to switches S
2
-S
7
, respectively, which may alternately be connected to point A which is connected to ground or to point B which is connected to switch S
8
. Switch S
8
may be alternately connected to point A which is connected to an input terminal for receipt of voltage V
IN
to be digitized, or to point B which is connected to a reference voltage terminal for receipt of a reference voltage V
REF
.
Analog-to-digital conversion is accomplished by three operations: sample, hold and redistribution. In sample mode, switches S
1
-S
7
are set to points B, and switch S
8
is set to point A. This grounds the top plates of capacitors
26
-
36
and charges their bottom plates to potentials proportional to the analog input V
IN
. In hold mode, switches S
1
-S
7
are set to points A, which disconnects line
14
from ground and connects the bottom plates of capacitors
26
-
36
to ground. Since the voltage cannot change instantaneously across capacitors
26
-
36
, the potential at analog summing node
42
goes to −V
IN
. Finally, in redistribution mode, the successive approximation technique is utilized to determine the data bits for the digital conversion.
Successive approximation begins by testing the value of the most significant bit (MSB). Switches S
2
and S
8
are set to points B, connecting V
REF
to the bottom plate of capacitor
26
. Switch S
1
remains in its A position. The remaining switches S
3
-S
7
remain set to points A. This establishes a voltage divider circuit between two equal capacitances, capacitor
26
(
16
C) connected between V
REF
and node
42
, and capacitors
28
-
36
(
8
C+
4
C+
2
C+C+C=
16
C) connected between node
42
and ground. The voltage V
X
(at summing node
42
which inputs to comparator
16
), which was equal to −V
IN
previously, is now increased by one-half the reference voltage V
REF
to V
X
=−V
IN
+V
REF
/2. Comparator
16
senses the polarity of V
X
and outputs a logic “1” if V
X
<0 and a logic “0” if V
X
>0. This determines the value of the most significant or 4th bit “b4”. Thus, MSB=1 if V
IN
>V
REF
/2 and MSB=0 if V
IN
<V
REF
/2. The output on conductor
18
(
FIG. 1
) is the value of the binary bit being tested. Switch S
2
is returned to point A (ground) if the MSB=0, or left at point B (V
REF
) if the MSB=1.
In a similar manner, the next MSB is determined by setting switch S
3
to point B to connect the bottom plate of the next largest capacitor (viz. capacitor
28
) to V
REF
, and checking the polarity of the resulting value of V
X
produced at node
42
. Here, the voltage division property of capacitor array
12
causes V
REF
/4 to be added to V
X
:
V
X
=−V
IN
+(b4×V
REF
/2)+V
REF
/4.
Comparator
16
will again output a logic 1 if V
X
<0 and a logic 0 if V
X
>0. This determines the value of the next most significant or 3rd bit “b3”. Thus, b3=1 if V
IN
>(b4×V
REF
/2)+V
REF
/4 and b3=0 if V
IN
<(b4×V
REF
/2)+V
REF
/4. The output on conductor
18
(
FIG. 1
) gives the value of the next MSB binary bit being tested. Switch S
3
is returned to point A (ground) if b3=0, or left at point B (V
REF
) if b3=1.
Conversion proceeds in this manner until all bits in the digital representation have been determined. The final configuration of the capacitor array
12
will have those switches S
2
-S
6
that correspond to bits of logic 0 set to point A, and those that correspond to bits of logic 1 left at point B. Thus, n redistributions are required for a conversion resolution of n bits. The logic outputs from comparator
16
serve as inputs to activate, control and sequence the positionings of switches S
1
-S
8
.
In the prior art, the most common method utilized for diagnostic testing of successive approximation ADCs is off-line testing. A known analog voltage input signal V
IN
is injected at the ADC input and converted to a digital value. The observed actual digital output word resulting from the conversion is then compared with the expected known correct digital result. If the actual digital output differs from the correct digital output, the components are trimmed, and the process repeated until the actual output matches the expected output to within acceptable tolerance. Such off-lin

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